In our one, two and three-day courses, which we conduct at technical and trade conferences as well as at private on-site classes, we will frequently be asked about particular technology trends and their impact on current designs. Of late, a number of these questions have focused on how the use of PCI Express (also known as PCIe) at higher frequencies impacts signals that change layers through vias. Limits on the number of vias in PCIe generations are well-known, but the effects of stubs and distributed parasitics are more difficult to see and are not often discussed.
This article will address layer-changing vias, which transpires with them relative to capacitance and how they can be best designed to avoid signal degradation. First, we will describe the various types of vias, the role of vias in PCIe layout, the speeds where layer-changing vias started to cause problems, and the overview of the different kinds of PCIe implementations. Later we will address how to solve the signal degradation issues associated with layer-changing vias. It will also explain how we used back drilling to solve the problem of getting a signal across two very thick PCBs without degrading it from loss or via reflections.
There are several appurtenant factors to keep in mind about vias relative to the topic of this article. They include:
The design/signal performance challenges associated with blind vias in PCIe routing started to occur once we got to speeds of 10 GB/s. The issue was first presented a few years ago at DesignCon because several product developers experienced many failures. In some cases, the problems described in this article can occur at much lower data rates.
The things to remember about layer-changing vias include:
The graphics which illustrate the foregoing are described below. The insertion loss on a transmission line with PCIe signals traversing vias is shown in Figure 1. These loss curves are for two 8” (20 cm) traces with 12 mils (.3 mm) drilled blind vias at each end.
Here, the red loss curve is for an eight-inch trace on L14 of a 16-layer PCB with the signal injected and measured on L1. The blue curve is for a trace on L3 with the signal injected and measured on L1.
The key thing to remember is that as you go up in frequency, the capacitive reactance decreases. There is a localized lowering of the impedance, and energy will reflect off of that lower impedance. And, if there are two of these, the energy will reflect back and forth between the two. This reflection can become so severe that it can result in large amounts of attenuation of the signal. This is shown in Figure 2, which is an equivalent circuit of vias in a transmission line.
Figure 3 shows TDR results for two different blind vias as they change layers. On the left is the TDR result for the trace traveling from L9 to L10 in a 22-layer PCB.
With the signal on the right side, when the signal travels, the via's parasitic capacitance is spread along its length (the inductance), and the via is negligible. On the left is the TDR result for the trace traveling between L9 to L10 in a 22-layer PCB. Here, the signal travels over only part of the via and the capacitance. That is not included in the path that (part of the via that is hanging down) forms the low pass filter and the frequencies can be blocked along with other similar vias.
As stated above, during our classes, we have gotten a number of questions regarding how the recent and current generation PCI speeds express standard impact layer changing vias. Below are a few salient points about PCIe.
The various flavors of PCIe include:
To be announced in 2021:
While PCIe is not used very much in backplanes, it is used in almost every server and every super high-performance gaming PC. We are aware of an imaging product under development that has PCIe all over it. It’s a piece of equipment used for the optical inspection of wafers. Even though this product is not a backplane, it will require back drilling just to accommodate all of the PCIe that is incorporated into the product.
In PCIe, where there are cards that plug into slots, the standard for those kinds of cards requires a via at every one of the pins. This is true even if you connect on L1. And, if you connect on this layer, you will wind up with a via hanging down. Hence, the term “boomerang via” was coined by Intel. In this configuration, right next to the via that is hooked right next to the connector, a second via is placed. The signal goes all the way to the bottom of the board, crosses over to the via that is part of the connector, and then goes back up. This is how the term “boomerang via” came into play.
Overall, the use of PCIe is going gangbusters. This is being forced, in large part, by all the graphic data that is included within 5G. In turn, this is forcing the developers of all the support equipment associated with 5G implementations to increase their bandwidth. This is why we tell developers that if they have not yet encountered the problems associated with high-speed PCIe and layer-changing vias it’s just a matter of time until they do so.
Changing gears, I will now address the fixes to the problems associated with layer changing vias and provide an example of how we resolved the challenge of getting a signal across two very thick PCBs with the use of back drilling.
The root of the problem associated with layer-changing vias is the parasitic capacitance that occurs when a signal travels over only part of a via. This capacitance forms a low pass filter along with other similar vias. At the speeds and frequencies associated with so many different products being developed for so many different vertical market segments, signals can become blocked.
Minimizing the foregoing via effects includes:
As with most things in life, there are drawbacks to the foregoing approaches. They include:
Figure 1 depicts how a blind person can access L2 as noted in the bullet point above.
In so doing, the effect of the via is held to a minimum. In addition, because the signals are routed on L2, the effects of the plating and etching associated with routing on L1 are eliminated. With this methodology, the capacitance of that 4-5 mil long via is trivial and is not apparent when measured. Product developers do have to ensure that there is enough room on L2 to implement this methodology. In addition, here, the through hole vias have been plugged, and the pads are covered with a solder mask. This is our preferred approach in dealing with layer changing vias to prevent cleaning solutions from getting under BGAs.
As noted previously, in backplanes, the only approach to handle layer-changing vias is to do back drilling because all signal layers may contain high-speed nets. With this technique, part of the plating in a through hole is removed. This reduces the parasitic capacitance between the via walls and the planes of the PCB. Back drilling is accomplished with all the standard processes used to manufacture through-hole PCBs. Once the fabrication processes are completed, the PCB is returned to the drilling station. A drill larger than the one used to drill the original hole is used to re-drill the holes where the plating is to be removed. The drill is set to a depth that removes the undesired plating while leaving the desired plating that makes the connections between the traces. While this adds an extra step to the fabricating process, it is not difficult to perform. It is necessary to keep in mind that the drill size needed to remove the unwanted copper will need to be several mils larger than the drill used to form the original hole. Thus, the clearances to the features in the plane and signal layers will need to be larger than when only through holes are drilled.
The benefits of back drilling can be shown through the following. Figure 2 depicts a test probe problem for which we provided consulting services.
Here, the challenge was to get a 3.6 GB/s signal across two very thick PCBs without degrading it due to loss or via reflections. Figure 3 shows the operation of the differential pair without back drilling and
Figure 4 depicts what the waveforms would be if back drilling was done.
As seen from the blue waveform in Figure 3, which is the receiver input, the results are disastrous. Figure 5 shows how the differential pair was used to simulate 36 mil (.762 mm) 250 mils (6.35 nm) long vias.
The full vias have a parasitic capacitance of about 1.3 pF. The simulation was down both with and without back drilling. Figure 6 is the simulated waveforms achieved with back-drilled vias.
Finally, Figure 7 shows the measured waveforms, which was wanted, with the back drilled vias.
The degrading signal effects from blind vias can be a significant challenge in designing today’s high bandwidth, high-speed products. This can be readily apparent when using the newer iterations of the PCIe bus standard, particularly when vias in PCIe routing are used to change layers. Some solutions here are back drilling, limiting via counts, sizing vias to have minimum impedance mismatch, and using boomerang vias. Learning how to mitigate these effects as part of the initial product development efforts will go a long way in ensuring that a product will function, right the first time and every time, as designed.