What Happens to Layer Changing Vias When Using PCI Express at Higher Speeds?
In our one, two and three-day courses, which we conduct at technical and trade conferences as well as at private on-site classes, we will frequently be asked about particular technology trends and their impact on current design undertakings. Of late, a number of these questions have focused on how the use of PCI Express (also known as PCIe) at higher frequencies impacts layer changing vias.
This article will address layer-changing vias, which transpires with them relative to capacitance and how they can be best designed to avoid signal degradation. First, we will describe the various types of vias, the speeds where layer-changing vias started to cause problems, and the overview of the different kinds of PCIe implementations. Later we will address how to solve the signal degradation issues associated with layer-changing vias. It will also explain how we used back drilling to solve the problem of getting a signal across two very thick PCBs without degrading it from loss or via reflections.
First, An Overview
What Are Vias?
There are several appurtenant factors to keep in mind about vias relative to the topic of this article. They include:
- Vias are the holes drilled through a PCB that provides electrical access from one layer to another.
- These drilled holes are plated with copper to provide the connections.
- A via has inductance and capacitance along its length, just like a transmission line.
- In theory, there are two kinds of vias, but we usually group them together.
- Vias may be used as component pins (through-hole or surface mount).
- Vias can also be plated through-holes for press-fit connectors (These are much larger than those used for component pins).
- Two of these vias occur for every path—one leaving the daughter card and the other going into the backplane or one leaving a component pin and connecting to another component pin on the same PCB.
- There is a “double whammy” when you have to go through a connector with a via because these vias are large compared to component pin vias.
- There are three kinds of vias—through-hole, blind, and buried vias.
- For this article, we are addressing blind vias.
- Blind vias begin on one side of the PCB but do not pass all the way through.
- The four ways to create blind vias are:
- Control depth drilling.
- Laser drilling.
- Sequential lamination.
- For this article, we are focusing on laser-drilled vias.
When Did Things Start to Get Dicey?
The design/signal performance challenges associated with layer-changing vias started to occur once we got to speeds of 10 GB/s. The issue was first presented a few years ago at DesignCon because several product developers experienced many failures. In some cases, the problems described in this article can occur at much lower data rates.
The things to remember about layer-changing vias include:
- When the signal travels the length of the via, the capacitance is distributed along the signal path as is the inductance.
- When the signal travels over only part of the via, the capacitance that is not included in path forms a low pass filter along with other similar vias and blocks the high frequencies in a given design.
The graphics which illustrate the foregoing are described below. The equivalent circuit of vias in a transmission line is shown in Figure 1. These loss curves are for two 8” (20 cm) traces with 12 mils (.3 mm) drilled vias at each end.
Here, the red loss curve is for an eight-inch trace on L14 of a 16-layer PCB with the signal injected and measured on L1. The blue curve is for a trace on L3 with the signal injected and measured on L1.
The key thing to remember is that as you go up in frequency, the capacity reactance goes down. There is a localized lowering of the impedance, and energy will reflect off of that lower impedance. And, if there are two of these, the energy will reflect back and forth between the two. This reflection can become so severe that it can result in large amounts of attenuation of the signal. This is shown in Figure 2, which is an equivalent circuit of vias in a transmission line.
Figure 3 contains the TDR results for two different layer-changing vias. On the left is the TDR result for the trace traveling from L9 to L10 in a 22-layer PCB.
With the signal on the right side, when the signal travels, the via's parasitic capacitance is spread along its length (the inductance), and the via is negligible. On the left is the TDR result for the trace traveling between L9 to L10 in a 22-layer PCB. Here, the signal travels over only part of the via and the capacitance. That is not included in the path that (part of the via that is hanging down) forms the low pass filter and the frequencies can be blocked along with other similar vias.
How Does PCI Express Fit In?
As stated above, during our classes, we have gotten a number of questions regarding how the recent and current generation PCI speeds express standard impact layer changing vias. Below are a few salient points about PCIe.
- The bandwidths double with each generation.
- A PCI connection consists of one or more lanes connected serially. The slots are configured in multiples of four lanes, such as x1, x4, x8, and x 16.
- The number of available PCIe lanes determines the bandwidth of a given slot.
- The number of lanes in a slot does not always match the physical slot length.
- Once the speeds of PCIe got up past 8 GB/s, there was the potential for product developers to encounter the aforementioned issues relative to layer-changing vias.
The various flavors of PCIe include:
- PCIe 1.0
- Lane Data Rate, 2.5 GB/s.
- Gigatransfer, 2.5 GT/s.
- Clock Frequency, 1.25 GHz.
- PCIe, 1.0/x4, x8, x 16.
- PCIe 2.0
- Lane Data Rate, 5 GB/s.
- Gigatransfer, 5 GT/s.
- Clock Frequency, 2.5 GHz.
- PCIe 2.0/4, x8, x 16
- PCIe 3.0
- Lane Data Rate, 8 GB/s.
- Gigatransfer, 8GT/s.
- Clock Frequency, 4 GHz.
- PCI 3.0/x 1, 4, 8, 16
- PCIe 4.0
- Lane Data Rate, 16 GB/s.
- Gigatransfer, 16 GT/s.
- Clock Frequency, 8 GHz.
- PCIe 4.0/x 1, 4, 8, 16
- PCIe 5.0
- Lane Data Rate 32 GB/s.
- Gigatransfer, 32 GT/s.
- Clock Frequency, 16 GHz
To be announced in 2021:
- PCIe 6.0
- Lane Data Rate, 64 GB/s.
- Gigatransfer, 64 GT/s.
- Clock Frequency 32 GHz.
While PCIe is not used very much in backplanes, it is used in almost every server and every super high-performance gaming PC. We are aware of an imaging product under development that has PCIe all over it. It’s a piece of equipment used for the optical inspection of wafers. Even though this product is not a backplane, it will require back drilling just to accommodate all of the PCIe that is incorporated into the product.
What’s a PCI Express Boomerang Via?
In PCIe, where there are cards that plug into slots, the standard for those kinds of cards requires a via at every one of the pins. This is true even if you connect on L1. And, if you connect on this layer, you will wind up with a via hanging down. Hence, the term “boomerang via” was coined by Intel. In this configuration, right next to the via that is hooked right next to the connector, a second via is placed. The signal goes all the way to the bottom of the board, crosses over to the via that is part of the connector, and then goes back up. This is how the term “boomerang via” came into play.
The Role of PCI Express Going Forward
Overall, the use of PCIe is going gangbusters. This is being forced, in large part, by all the graphic data that is included within 5G. In turn, this is forcing the developers of all the support equipment associated with 5G implementations to increase their bandwidth. This is why we tell developers that if they have not yet encountered the problems associated with high-speed PCIe and layer-changing vias it’s just a matter of time until they do so.
Changing gears, I will now address the fixes to the problems associated with layer changing vias and provide an example of how we resolved the challenge of getting a signal across two very thick PCBs with the use of back drilling.
So, What’s the Fix?
The root of the problem associated with layer-changing vias is the parasitic capacitance that occurs when a signal travels over only part of a via. This capacitance forms a low pass filter along with other similar vias. At the speeds and frequencies associated with so many different products being developed for so many different vertical market segments, signals can become blocked.
Minimizing the foregoing via effects includes:
- Making sure the signals travel the whole length of the via by placing the signals on the lower layers of the PCB.
- Beginning and ending the signal on L1 and using no vias.
- Using vias at both ends of the signal when routed on layers near the top of the PCB and back drilling that portion of the via that extends below the trace layer.
- Routing the signal on L2 and entering and exiting the trace using a laser-drilled blind via.
As with most things in life, there are drawbacks to the foregoing approaches. They include:
- It’s only possible to limit signals to the lower layers if the number of signals routed does not exceed what can be put on the lower layers.
- Routing signals on L1 without using vias only works if those signals will fit into the available space. As noted previously, PCB outer layers have the poorest impedance accuracy. Plating the signals with ENIG (electroless nickel immersion gold) results in much higher loss than anticipated because of the nickel’s ferromagnetic properties.
- Back drilling away the unwanted portion of the via that extends below the trace layer requires an extra step in the process, and it also increases cost. Moreover, there is a risk of drilling too deep and breaking the connection to the trace. However, in some instances, as noted below, back drilling is the only way to go.
- Routing the signals on L2 and using blind vias to make the connection yields the best signal quality but requires an extra process step that can also increase the cost.
Figure 1 depicts how a blind person can access L2 as noted in the bullet point above.
In so doing, the effect of the via is held to a minimum. In addition, because the signals are routed on L2, the effects of the plating and etching associated with routing on L1 are eliminated. With this methodology, the capacitance of that 4-5 mil long via is trivial and is not apparent when measured. Product developers do have to ensure that there is enough room on L2 to implement this methodology. In addition, here, the through hole vias have been plugged, and the pads are covered with a solder mask. This is our preferred approach in dealing with layer changing vias to prevent cleaning solutions from getting under BGAs.
A Few Words about Back Drilling
As noted previously, in backplanes, the only approach to handle layer-changing vias is to do back drilling because all signal layers may contain high-speed nets. With this technique, part of the plating in a through hole is removed. This reduces the parasitic capacitance between the via walls and the planes of the PCB. Back drilling is accomplished with all the standard processes used to manufacture through-hole PCBs. Once the fabrication processes are completed, the PCB is returned to the drilling station. A drill larger than the one used to drill the original hole is used to re-drill the holes where the plating is to be removed. The drill is set to a depth that removes the undesired plating while leaving the desired plating that makes the connections between the traces. While this adds an extra step to the fabricating process, it is not difficult to perform. It is necessary to keep in mind that the drill size needed to remove the unwanted copper will need to be several mils larger than the drill used to form the original hole. Thus, the clearances to the features in the plane and signal layers will need to be larger than when only through holes are drilled.
The benefits of back drilling can be shown through the following. Figure 2 depicts a test probe problem for which we provided consulting services.
Here, the challenge was to get a 3.6 GB/s signal across two very thick PCBs without degrading it due to loss or via reflections. Figure 3 shows the operation of the differential pair without back drilling and
Figure 4 depicts what the waveforms would be if back drilling was done.
As seen from the blue waveform in Figure 3, which is the receiver input, the results are disastrous. Figure 5 shows how the differential pair was used to simulate 36 mil (.762 mm) 250 mils (6.35 nm) long vias.
The full vias have a parasitic capacitance of about 1.3 pF. The simulation was down both with and without back drilling. Figure 6 is the simulated waveforms achieved with back-drilled vias.
Finally, Figure 7 shows the measured waveforms, which was wanted, with the back drilled vias.
The degrading signal effects from layer-changing vias can be a significant challenge in designing today’s high bandwidth, high-speed products. This can be readily apparent when using the newer iterations of the PCI Express bus standard. Learning how to mitigate these effects as part of the initial product development efforts will go a long way in ensuring that a product will function, right the first time and every time, as designed.
- Ritchey, Lee W. and Zasio, John J., “Right The First Time, A Practical Handbook on High Speed PCB and System Design,” Volume 2.
- Ritchey, Lee W., Course Slides, “2-Day Signal Integrity and High Speed System Design,” training class.