Here and in several other articles published on the Altium Resource section of the company’s website, the topic of transmission line impedance has been addressed from a number of different perspectives. I have addressed transmission line impedance previously in my article, The Evolution Of Simulation Technology and Impedance and, it might seem that we may have exhausted the field of potential information that can be provided on impedance, however, in truth, some features were only addressed in passing. This article will elaborate on those features and their effects along with basic equations that are used in controlling transmission line impedance.

As discussed in previous articles, the four main variables that determine the impedance of a transmission line on a surface layer include:

- Height of the trace above the plane over which it travels.
- The width of the trace.
- The thickness of the trace.
- The insulating material used to support the trace.

Once the above four variables are known, it is possible to determine which features in a PCB will have a relevant effect on impedance. These features include:

- Changes in trace width in the same layer. This is generally referred to as trace necking.
- Trace necking refers to the reduction of the trace width when it approaches a narrower pad such as that found on an SMD (surface mount device) or a through-hole that has a diameter that is less than the width of the trace.

- Changes in trace thickness.
- Changes in height above the plane.
- Stubs along the transmission line.
- Loads along the transmission line.
- Connector transitions.
- Poorly-matched terminations.
- No terminations.
- Larger power plane discontinuities.
- Changes in the relative dielectric constant.

As noted in previous articles, right-angle bends and vias are not on the above list because neither one of these features is a significant source of impedance mismatch.

There are a few equations that are helpful in calculating impedance. They are presented below. As noted previously, the impedance of a transmission line is determined by the capacitance and inductance that is distributed along the length of the transmission line. And, the equation used for calculating impedance is repeated here in Equation 1.

*Equation 1. The Impedance Equation*

In the above, Z_{0} is the impedance in ohms; jωL_{0} is the parasitic inductance in henrys per unit length, jωC_{0} is the parasitic capacitance in farads per unit length and R_{0} is skin effect loss (which can be ignored until you get to very high frequencies). G_{0} is the loss in the dielectric. As noted above, changing either the parasitic inductance or the parasitic capacitance will change the impedance of the transmission line. It’s also been demonstrated that changes in impedance cause signal reflections. For convenience, the reflection equation is repeated in Equation 2.

*Equation 2. The Reflection Equation*

This equation predicts the percentage of the incident EM field that will be reflected back to the source based on the two impedances on each side of a change where Z_{l} is the downstream impedance and Z_{0} is the upstream impedance. The equation reflects the voltage amplitude of the reflection.

Based on Equation 1, it is not obvious which variables will have an effect on impedance. Equation 3 is the classic surface microstrip equation. It illustrates the variables in a PCB that determine impedance.

*Equation 3. The Classic Surface Microstrip Impedance Equation*

This equation is included for illustration purposes only so that the variables can be shown. In a separate article following this one, it will be shown that this equation as well as other equations used to calculate impedance have a limited range over which they are valid. More accurate methods are available and some have been discussed in previous articles. The article following this one will also contain other methods for determining impedance.

The common characteristics of the features noted above is that they can have a measurable effect on one or both of the variables in Equation 1, parasitic inductance or parasitic capacitance. We can take those features and show the variables that they affect.

- Change in trace width in the same layer—C
_{0} - Change in trace thickness—C
_{0} - Change in trace height above the plane—C
_{0} - Stubs along the transmission line—C
_{0} - Loads along the transmission line—C
_{0} - Connector transitions—C
_{0} - Large power plane discontinuities—C
_{0} - Changes in relative dielectric constant—C
_{0} - Poorly matched terminations
- No terminations

As can be seen, with the exception of poorly matched terminations and no terminations, all of the sources of impedance mismatch are caused by something that changed the parasitic capacitance. Within the limits of trace dimensions in PCBs, compared to C_{0}, L_{0} is relatively constant. This helps when it comes time to design controlled impedance signal paths or troubleshoot impedance problems.

Once it is understood that virtually all impedance changes along the length of a transmission line are due to changes in parasitic capacitance, it becomes easier to manage those changes and create good impedance control.

Table 1 shows the relative dielectric constant of the laminate that is commonly known as FR-4.

*Table 1. Laminate Information for Laminate Commonly Called FR-4*

Not only does the relative dielectric constant change with frequency, it also varies with the amount of glass and resin used to make the laminate. As can be seen, there are four ways to make a 4-mil thick piece of laminate; three ways to make a 5-mil thick piece of laminate and four ways to make a 6-mil thick piece of laminate. Also, note that the ratio of glass to resin is different in each of these formulations as is the relative dielectric constant. If a PCB stackup is designed to use one of these formulations and the fabricator uses one of the others, the impedance will not come out as expected. This is the most common reason that changing fabricators results in PCBs with different characteristics. To avoid this problem, it is necessary to specify, on the fabrication drawing, which laminate formulation is required in each opening in the stackup.

Understanding the variables and features within a PCB that can affect transmission line impedance makes it easier to design for impedance control right the first time, and easier to troubleshoot any impedance issues that may occur during the design or during the fabrication processes.

Have more questions? Call an expert at Altium or read on to learn more about incorporating impedance calculations into your design rules with Altium Designer^{®}.

- Ritchey, Lee W. and Zasio, John J., “Right The First Time, A Practical Handbook on High-Speed PCB and System Design, Volume 1.”