In Part 1 of this article, I reviewed the four basic types of PCB transmission lines and the various equations used for calculating the impedance associated with those lines. Part 1 also discussed why those equations only tell part of the story, and why there are other influencers including 2D field solvers; knowing the glass-to-resin ratio and knowing the frequency at which transmission lines will be used that impact the process of ensuring that the calculated impedance matches the measured impedance.
There are additional aspects that play a role in determining impedance, such as what frequency should be used to calculate and measure impedance; impedance vs. height above the nearest plane, and wave velocity vs. location in the PCB. They are discussed in order below.
As noted in Part 1 and other articles, impedance in a PCB varies with the frequency at which the measurement is made. This leads to the question, what frequency should be used in the design process? Most transmission lines in PCBs are intended for logic signals and those logic signals do not operate at a single frequency. Instead, they are a collection of rising and falling edges and it is those rising and falling edges that can potentially become sources of reflections if impedance is not properly managed. The question then becomes how do you get from edge to frequency? This is accomplished by performing a mathematical operation on a switching edge of some rise time, referred to as tr. This operation is called a Fourier transform, and is done on a voltage waveform, then converted from the time domain to the frequency domain (or the reverse). When this conversion is done, it is possible to determine what frequencies are of interest for the impedance calculation. There will be a spectrum of frequencies that begin at what is often referred to as the first harmonic of the switching edge along with the odd harmonics of this frequency. Most of the energy of interest will be in the first harmonic and it is this frequency that will be used to calculate impedance. Equation 1 yields a reasonable approximation of this first harmonic.
Equation 1. Formula for Estimating the First Harmonic of a Switching Edge
From the foregoing equation, it can be seen that the first harmonic of 350 pSec edge is 1 GHz. As this is very far from the 1 MHz value used to characterize many laminates, the fastest edge that will travel on the transmission line should be used for impedance calculation. For most logic currently being supplied to designers, the rise times are at or below 100 pSec. This results in a first harmonic above 3 GHz. If one examines the dielectric constant of almost all laminate systems it can be seen that the dielectric constants do not change significantly above 2GHz. Therefore, using the dielectric constant listed at 2GHz will produce impedances that are accurate.
As we have noted previously, 50 ohms is used for PCB impedance. Then the next question is why can’t 65 or 70 ohms be used? The answer lies in the limitations of materials and processes and the layer requirements for PCBs. Figure 1 shows the impedance that is achieved with a 5-mil wide trace in the three types of transmission lines, SMS, BMS and CSL identified in Part 1 of this article.
Figure 1. Impedance vs. Height Above Plane for Three Types of Transmission Lines
This trace width has been chosen as the narrowest trace width that can be practically achieved in volume manufacturing operations. In Figure 1, the height above the nearest plane has been increased from 5 to 20 mils to see how high the impedance can be on each of the aforementioned three layer types.
Even with the narrowest production trace width, stripline layers cannot achieve high impedance. In all instances, high impedances require very thick dielectrics which make PCBs excessively thick as well as subject to severe crosstalk.
If the only signal layers in a PCB are surface microstrip, it is possible to have impedances ranging from 65 ohms to 113 ohms. 50 ohms would only be possible if the height above the plane were reduced to less than 5 mils but on the low end of practical material thickness. As soon as more than two signal layers are needed, the additional layers will have to be buried microstrip or stripline. If BMS is chosen, it’s possible that impedances can range from 58 to 101 ohms so the highest impedance that could be achieved is still quite high. However, adding the BMS layer forces the surface microstrip layer farther away from the plane and it would be difficult if not impossible to make the impedance of the two layer types the same.
If four or more routing layers with the same impedance are needed, all but two of them have to be CSLs. In this configuration, the possible impedances range from 42 ohms to 80 ohms. So, it would be possible to create a PCB with signal layer impedances up to 80 ohms. However, the dielectric thicknesses would have to be very large resulting in a very thick PCB; the crosstalk would also be excessively high.
Taking into account the constraints of crosstalk and reasonable PCB thickness, dielectrics should be kept under 6 mils. Given this constraint, it is not possible to achieve impedances higher than 55 ohms on stripline layers. This forces the impedance on the BMS layers to be the same.
In creating PCB stackups that balance the needs of manufacturability, crosstalk and impedance against each other, it becomes clear that a 50-ohm impedance is the best compromise. Impedances higher or lower than this will be difficult to achieve. For example, if there is a requirement for a 38-ohm impedance, as required by Rambus, manufacturability will be compromised. Similarly, if the 65+ ohms required by some protocols are used, the result will be excessive crosstalk.
From an economic standpoint, it is desirable to use as many PCB signal layers as possible for high speed signals. Sometimes, it is asserted that the only layers good enough for such signals are the stripline layers. If this is so, buried microstrip and surface microstrip signal layers are not usable. This means that additional signal layers will be required and the resulting PCB will cost more. Therefore, to use the signal layers in a PCB interchangeably, there are three requirements that must be met. They include:
Figure 2 shows a plot of signal velocity vs. relative dielectric constant for the usual range of materials used to build PCBs. The left axis is the velocity in inches per nanosecond and the right axis is the reciprocal or picoseconds per inch.
Figure 2. Signal Velocity vs Relative Dielectric Constant
These two scales allow for easy conversion from relative dielectric constant to either unit of measure. These graphs were created by using Equation 2.
Caption: Equation 2. Velocity vs. Relative Dielectric Constant
C = Speed of Light, V = Velocity in Dielectric, er = Relative Dielectric Constant
On the left hand side of this graph is the stackup of an eight-layer PCB. Here, the short bars represent the signal layers while the long bars represent the planes. This PCB has two SMS layers, two BMS layers, two CSL layers, and two planes. Part of the production test for this PCB involved impedance and velocity for each layer and the velocity of each layer has been plotted. The velocity of the SMS layers was measured at 154 picoseconds per inch; the BMS layers at 167 picoseconds per inch; and the CSL layers at 171 picoseconds per inch. The effective dielectric constant for each of these three layers is 3.33, 3.87 and 4.05 respectively. The velocity of the BSM is virtually the same as the CSL layer. They are so close that it would be difficult to measure a difference. Thus, one of the interchangeability goals has been met. In order to use them interchangeably, they have to be of the same impedance, which can be accomplished through careful selection of the trace width. As a result of the foregoing, BMSs and CSL layers can be used interchangeably for high speed signals.
Figure 3 illustrates the most common method to measure PCB trace impedance. This is where the TDR (time-domain reflectometer) noted in Part 1 of this article comes into play.
Figure 3. A Time Domain Reflectometer (TDR) Set Up to Measure Impedance
A TDR is really two instruments in one. A pulse generator produces signals with very fast rising edges. These signals are sent out on the test cable to the trace under test. Attached to the output port of the TDR is a sampling oscilloscope that is capable of responding to very fast signal transitions. This oscilloscope monitors the voltage at this point. The screen can display the signal that is sent out of the instrument and all of the reflections that occur from changes in impedance along the structure under test. Reflections from impedance changes in the impedance of a trace under test are measured. The size of the signal and polarity of the signal that is reflected is measured. Knowing that the test cable and the test output are 50 ohms, it is possible to use Equation 3 to calculate the impedance of the trace under test.
Equation 3. “The Reflection Equation”
Most TDRs have Equation 3 built into the operating software. All the person operating the TDR needs to do is place a cursor on the point of interest on the test trace, and the instrument makes the measurements, does the calculations and displays the impedance. Some instruments, such as those from Polar Instruments, have additional features on the screen that show the maximum allowable impedances. This creates a “go/no go” criterion that makes rapid production testing easy. These tools also have a data logging capability that produces the test records as part of a test report.
Just as accurately calculating impedance requires a statement for the frequency at which the impedance is being calculated, accurately measuring impedance has the same potential error in terms of the rise time of the test signal. For example, if the impedance is designed for a 500-picosecond edge and the impedance is measured with a 40-picosecond edge, there will be two different impedances. Table 1 shows that measured impedance varies significantly as the rise time of the test edge is changed.
Table 1. Impedance vs Rise Time of Test Signal Edge
Specifying the rise time of the edge used to test impedance is as important as all of the other
parameters involved in calculating impedance.
It is important to agree upon on the rise time of the test edge as part of the test specification for a controlled impedance PCB. This rise time must be within the range of rise times that can be produced by the equipment. Since most PCB fabricators manufacturing controlled impedance PCBs now have production test equipment with a 40 picosecond rise time, it is recommended that the rise time of the test edge be in the range of 15 to 40 picoseconds. While not ideal, it is a reasonable compromise to account for the differences between the equipment available to engineers and the equipment available to manufacturers.
Correct calculation and measurement of transmission line impedance is accomplished through a variety of means, including equations, 2D field solvers, and TDRs. Each of these plays a significant role in the impedance calculation and measurement process, and should be utilized as an integral part of the PCB design process.