MIPI Physical Layer Routing and Signal Integrity

MIPI physical layer routing (C-PHY) is typically used to connect these smartphone cameras to a processor.

When most designers talk about routing standards, particularly for advanced devices, they typically refer to differential routing standards (e.g., LVDS) that enable high data rates. These signaling standards have proliferated computers, networking equipment, smart electronics, and other areas, and they have been critical for operating with higher data rates alongside relative noise immunity. In mobile devices and other products that require high transfer rates when working with image and video data, peripheral routing typically uses an alternative set of physical layer specifications for routing.

The MIPI physical layer standards are popular in smartphones and other mobile devices, but the range of applications is quickly expanding into new areas. In October, the MIPI Alliance announced new activities focused on advanced driver assistance systems (ADAS), autonomous driving systems (ADS), and other automotive applications. Another upcoming area where MIPI will become indispensable is computer vision (i.e., robotics). PCB designers, SoC designers, and OEMs should stay aware of these developments. In particular, PCB designers outside the smartphone industry will need to become very familiar with MIPI physical layer routing.

PHY Standards and Interfaces

The mobile industry processor interface (MIPI) is a set of industry specifications designed for mobile devices, including smartphones, laptops, tablets, and IoT products. The MIPI standards define interfaces and physical layers; interfaces define how devices communicate with each other over a specific signaling standard, while the physical layer specifications (as its name implies) define how signals are routed between an MCU/MPU and a MIPI-capable device.

Sensors, imaging components, peripherals, and SoCs built to use different interfaces can take advantage of different physical layers for certain applications. The three MIPI physical layer standards are D-PHY, C-PHY, and M-PHY. Each of these was intended for different applications, and component/peripheral designers have implemented the corresponding interfaces accordingly.

MIPI M-PHY is designed to provide communication channels in data-intensive applications. Some examples include transfer and processing of high resolution images, high frame rate and resolution video, and data transfer between mobile displays and memories. D-PHY is more often used in smartphones cameras and displays as it provides high speed communication between a device and its processor. This particular physical layer and its associated interfaces are also used in automotive systems, particularly automotive radar, cameras, infotainment systems, and dashboard display units.

MIPI C-PHY was designed for mobile cameras and displays, although it has also found a home in wearables, IoT camera systems, and automotive displays/cameras. C-PHY can share the same physical layer and device pins as D-PHY, meaning designers can use an SoC that operates in both modes.

MIPI physical layer characteristics. Image from the MIPI PHY Tech Brief.

Routing in MIPI Physical Layers: C-PHY vs. M-PHY and D-PHY

D-PHY and M-PHY use typical differential signaling; M-PHY uses an embedded clock while D-PHY uses a source-synchronous clock. C-PHY, however, uses a more complex differential signaling scheme with three pins per lane. The C-PHY signaling standard uses 3 signal levels which are sensed differentially, similar to bipolar-RZ. This interesting scheme requires 50 Ohm characteristic impedance for each line and 100 Ohm differential impedance between each line with 3 lanes in total. Just like typical differential signaling, this requires tight coupling between lines as they are routed between a processor and a device.

The differential common mode noise filter used in C-PHY is unique in that you cannot use a set of 3 separate common mode noise filters as this will distort the signal levels. Using standard differential common mode noise filters will destroy the signal level in C-PHY and will not remove common mode noise from all three lines simultaneously. Instead, specialized common mode noise filters with three input and three output pins are required for noise filtration.

Despite the use of three differential signaling lines, these lines must be length matched on the PCB to ensure rising edges in each line coincide in order to accurately detect signal levels and suppress common mode noise. C-PHY encoding is designed to guarantee that there is at least one rising edge per symbol and that the differential input in all three received signals is non-zero. Compared to D-PHY, C-PHY uses fewer traces, fewer edge transitions, fewer lanes, and less board area for the same data transfer rate. In addition, because the clock is embedded in C-PHY and there is always a signal transition, there are no additional radiated emissions from a dedicated clock lane and clock recovery at the receiver is much easier.

Signal levels on the three differential lines in MIPI C-PHY

A C-PHY component that receives senses signals differences between two of the three lines at a time, requiring a total of three differential receivers integrated into the receiving IC. Each receiver looks at the signal difference between two of the three signals, producing a base-5 signal system. Because C-PHY works with edge transitions at the receiver rather than typical signal levels, it is less sensitive to losses in the signal level than typical signaling techniques.

Example: CSI-2 Routing

MIPI CSI-2 is most commonly implemented on C-PHY to provide high-speed data from a camera to a processor, such as a webcam. The standard is a mixed serial-parallel interface that operates as follows:

• All interconnects are routed on the PCB as differential pairs
• The interface contains a dedicated source-synchronous clock
• The interface contains up to 4 data lanes; typically either 2 or 4 are used.
• The interface has timing restrictions that demand length tuning
• The differential impedance requirement is 100 Ohms
• Data rate is limited to 2.5 Gbps per lane

With a maximum data rate of 10 Gbps over 4 lanes, this standard satisfies the requirements of commercially available high-resolution cameras. The advantage of this interface being spread across 4 lanes is that the channel bandwidth requirement is quite low, thus the interface is very robust against impedance discontinuities from vias and connectors.

The image below shows an example of CSI-2 routing in an internal layer of a PCB (differential striplines). As a mixed serial-parallel interface, the use of length tuning in a pair and between pairs is a hard requirement; the routing shown below has individual length tuning sections applied in each differential pair, as well as larger sections that length tune across the entire group. The routing follows the standard differential pair rules and guidelines.

CSI-2 routing example. This example uses 4 data lanes and a clock lane to transfer high-speed serial data from a camera to an FPGA in this example. The traces are directly routed between the two ends of the link without coupling capacitors.

Are there other interfaces where this type of high-speed serial/parallel mixed bus routing exists? Aside from D-PHY with CSI-2, you can also find this type of routing in the JESD204C interface for high-speed ADCs used in RF systems; the topology in this style of routing is almost identical to that used in CSI-2. If you recall DDR, it essentially operates the same way, where a source synchronous clock is routed alongside a set of data lines and other lines, the difference is that DDR mixes single-ended and differential routing into the same interface.

Another instance where a similar type of routing is implemented is with differential interfaces instantiated over LVDS, such as in an FPGA or in some high-speed ASICs. This is less common, but once again the PCB routing for the differential interface is implemented with length matching within a single differential pair, as well as length matching across the group of differential pairs. No matter what you need to design or route, the best routing tools in your PCB design software can keep you productive and help you route these advanced interfaces quickly.

Whether you are working with MIPI physical layer specifications or other signaling standards, the routing and layout tools in Altium Designer^® are ideal for creating your next mobile, IoT, automotive, or hybrid device. These tools are built on top of a unified rules-driven design engine, allowing you to define routing specifications as design rules and check them automatically as you create your layout.

Now you can download a free trial of Altium Designer and learn more about the industry’s best layout, simulation, and production planning tools. Talk to an Altium expert today to learn more.