What is the JESD204C Standard for ADCs/DACs?

Zachariah Peterson
|  Created: November 9, 2022
JESD204C Standard for ADCs

Table of Contents

Serial interfaces have had difficulty keeping pace with the needs of high sample rate data converter components, namely ADCs and DACs. One option for doing this was formerly LVDS links between data converters and a host controller. These links would provide high data rates over differential pairs to a single device, offering high throughput data transfer from fast-sampling ADCs. Later, JEDEC released the JESD204 specification, and it has since been incorporated into many components as a data converter interface.

The most recent iteration of the JESD204 interface standards, currently JESD204C, brings extreme data rates to fast ADC/DAC components that are used to sample signals at very high sample rates. Now that the newest iteration of the standard has been around for just over 2 years, there are many components available that can be used with FPGAs to provide ultra-fast sampling, transmission, and DSP in RF systems.

Overview of JESD204C

The JESD204C standard is the newest iteration of the general JESD204 standard, which is published and maintained by JEDEC. The standard was developed to replace the use of LVDS links between data converters and their system hosts. It defines a serial interface and protocol used in high sample rate ADCs/DACs for signal sampling, synthesis, and synchronization. The synchronization aspect is important for this interface as it allows a single host controller to synchronize signal sampling and synthesis across multiple devices.

Some of the primary operating parameters implemented in the physical layer are listed in the table below. The current JESD204C iteration improves on the data rate and encoding characteristics of the previous JESD204B iteration, which used 8b/10b encoding with maximum data rate of 12.5 Gbps. This interface can be found in ADCs/DACs that operate anywhere from 100 MSps to 1 GSps or higher.

Operating parameter

Value

Interconnect type

SerDes w/embedded clock, multiple lanes

Maximum data rate

32.5 Gbps per lane

Encoding

  • 64b/66b standard
  • 64b/80b and 8b/10b supported

Impedance

100 Ohm differential (AC or DC coupled)

Multi-device synchronization

System reference oscillator or 1 sync pin per device

Equalization

FIR (Tx device), CTLE, DFE, 

 

Example Topology

The topology of a JESD204C interface depends on the Subclass of the interface. JESD204B introduced Subclasses 1 and 2 to implement a synchronization strategy known as deterministic latency. This strategy achieves synchronization across devices by determining the phase mismatch between data streams being transmitted to the host controller.

  • Subclass 0 - No deterministic latency support (backward compatible with JESD204A)
  • Subclass 1 - Deterministic latency achieved using an external reference oscillator (SYSREF) as timing signal
  • Subclass 2 - Deterministic latency achieved using a SYNC pin between the host controller and the ADC/DAC

Two implementations of the interface are shown in the graphic below.

JESD204C subclasses
JESD204B/C Subclass 1 and Subclass 2 topologies.

DATA1 and DATA 2 are routed as differential pairs; each lane in these I/O groups is a differential pair and a given device could have multiple lanes (some products have up to 8 per device). In both Subclasses, the clock source is routing to all devices in a source-synchronous manner. Timing and deterministic latency are achieved in each Subclass by appropriate matching of SYSREF and DCLK/SYNC to setup-and-hold times, as well as to each other when distributed across multiple data converters.

Routing, Deskew, and Latency

Deterministic latency was mentioned above: this is the technique by which a single host controller can synchronize data collection and synthesis across multiple devices with precise timing such that the timing skew between sampling frames is known. This is corrected by tuning trace delays to each other so that delays between them are matched. A JESD204B or JESD204C interface uses delay matching in the control bits being sourced from SYSREF (in Subclass 1) or from the SYNC pins (in Subclass 2).

The table below outlines the length/delay matching requirements in the timing signals for each Subclass in the JESD204B and JESD204C interfaces.

Subclass 1

Subclass 2

Each DCLK + SYSREF pair matched to setup-and-hold times

DCLK is used as device clock, no SYSREF for frame alignment

DCLK and SYSREF pairs are matched to each other across all devices

DCLK nets are matched to each other across all devices

SYNC only triggers code group synchronization and is not critical for timing

SYNC routed in point-to-point topology for code group synchronization

SYNC routed in bus topology

SYNC nets not required to be matched to each other, but must comply with DCLK setup-and-hold times for each device

 

The main difference here is how the SYNC nets are treated. In Subclass 1, these nets are only used for code group synchronization, while they are also used for timing in Subclass 2. Therefore, JESD204C has fewer signals for a given number of I/O channels in the data converters.

Why JESD204C vs LVDS?

The advantage of the JESD204C interface for high-speed sampling and synthesis at GHz frequencies is this ability to eliminate skew and latency mismatch across multiple converters. There is some skew budget for any JESD204 interface, which is the maximum amount of skew that can be compensated in the system timing scheme in order to guarantee deterministic latency within the limits of phase noise. The goal is to ensure the host controller knows the phase mismatches of the resulting incoming data streams and can compensate for it in logic, thus establishing the true timing between the sampled signals.

The other reason for the use of JESD204C is that it reduces the routing and timing requirements in the PCB layout. In a typical implementation, the DATA1 and DATA2 differential pairs coming from Device 1 and Device 2 will have some skew between them. With LVDS, this would require matching differential pairs running in parallel to each other. In JESD204C, we only need to eliminate skew across the DCLK and SYSREF/SYNC nets, but not the data nets across devices. This makes the interface essential in high-density mixed-signal devices.

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About Author

About Author

Zachariah Peterson has an extensive technical background in academia and industry. He currently provides research, design, and marketing services to companies in the electronics industry. Prior to working in the PCB industry, he taught at Portland State University and conducted research on random laser theory, materials, and stability. His background in scientific research spans topics in nanoparticle lasers, electronic and optoelectronic semiconductor devices, environmental sensors, and stochastics. His work has been published in over a dozen peer-reviewed journals and conference proceedings, and he has written 2000+ technical articles on PCB design for a number of companies. He is a member of IEEE Photonics Society, IEEE Electronics Packaging Society, American Physical Society, and the Printed Circuit Engineering Association (PCEA). He previously served as a voting member on the INCITS Quantum Computing Technical Advisory Committee working on technical standards for quantum electronics, and he currently serves on the IEEE P3186 Working Group focused on Port Interface Representing Photonic Signals Using SPICE-class Circuit Simulators.

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