Modeling Copper Foil Roughness in Altium Designer's Impedance Profiler

<p>Advanced transmission line models for long interconnects require that designers include copper foil roughness calculations in order to determine accurate impedance. Without the right models or design software, you’ll be left to estimate the skin effect impedance, dispersion, and parasitics in your PCB. These models can be difficult to work with by hand if you’re not mathematically inclined, but the right design tools can be used to quickly incorporate copper roughness in your impedance profiles as you create your stackup.</p>

<p>With the new layer stack manager in Altium Designer®, you can now include copper foil roughness factors directly in your <a href="https://files.resources.altium.com/sites/default/files/2020-03/Impedanc… calculator</a>. This is quite easy to do in the layer stack manager, but it begs the question: what exactly is the copper roughness factor? Which value should be used for your interconnects? This is a complex question that relates to copper deposition processes on cores and laminates. However, with some reasonable approximations in two standard models for copper roughness, you can calculate a reasonable copper roughness factor value in Altium’s impedance profiler.</p>

<h2><a id="impedance-profiles-in-your-pcb-stackup">Impedance Profiles in Your PCB Stackup</a></h2>

<p>The impedance profiler in Altium Designer includes an integrated electromagnetic field solver, which calculates transmission line impedance profiles at a desired reference frequency. This solver uses the roughness, Dk, and Df values to determine an impedance value for microstrips, striplines, and coplanar geometries (both single-ended and differential). This causal solver gives the impedance assuming very high frequency propagation where the impedance begins to saturate to a fixed value and begins to become insensitive to frequency.</p>

<p>When it comes to modeling resistive and inductive losses due to the skin effect, there are two factors to consider:</p>

<ul>
<li><strong>Interconnect cross-sectional geometry</strong>: The cross-sectional dimensions of your traces determine the <a href="https://resources.altium.com/p/copper-choice-and-copper-efficiency-high… depth for AC signals</a>. This creates resistive and inductive impedance contributions to the characteristic impedance.</li>
<li><strong>Surface roughness and morphology of the deposited copper</strong>: Real electrodeposited copper is not smooth, and is instead created from accumulated chunks of material. In addition, etching during manufacturing will roughen the surface, which increases losses that would normally occur due to the skin effect.</li>
</ul>

<p>The first point above can be easily included using the standard equations from electromagnetism. Modeling the second point requires accounting for the internal morphology of the copper trace, as well as the average surface roughness of the trace. If you want to work with the standard circuit model for transmission line impedance, then you’ll use the following equation to include the impedance contributions from copper roughness:</p>
<img alt="Copper foil roughness and impedance in a PCB transmission line" data-align="center" data-caption="&lt;em&gt;Real interconnect impedance due to the skin effect and roughness&lt;/em&gt;" data-entity-type="file" data-entity-uuid="a4f6b3c4-1fe1-4e69-9e76-2e2ab0e95a50" data-responsive-image-style="" src="/sites/default/files/inline-images/copper-rough-2_0.png">
<p>The R(rough) resistance term is related to the skin effect and the roughness of the copper used to form transmission lines. Accounting for the morphology requires developing some models which are specific to the arrangement of copper particles and their sizes.</p>

<p>Roughness correction factors can generally be used in a PCB-specific field solver, such as <a href="https://resources.altium.com/p/simberians-3d-field-solver-in-altium-des… Designer’s integrated field solver from Simberian</a>. Other field solvers for full 3D solutions can be used in The roughness correction factor you use in Altium Designer’s impedance profiler needs to be determined using a causal representation. This can easily be calculated using the Hammerstad or Cannonball-Huray models, although there are many other models available that are being incorporated into EDA tools.</p>

<h2><a id="calculating-copper-foil-roughness-correction-factors">Calculating Copper Foil Roughness Correction Factors</a></h2>

<p>The widely accepted models for calculating roughness correction factors are the Cannonball-Huray and Hammerstad models. The Cannonball-Huray model has more power and adaptability in terms of fitting to experimental data, but its form is more complex. However, enforcing causality in this model does yield a closed-form expression for the roughness correction factor in this model. The main input in the model is a measurement of the average copper particle size in a trace (called a cannonball in this model).</p>

<p>In contrast, the Hammerstad model provides a closed-form equation for the copper roughness correction factor, which is a function of surface roughness. This makes the Hammerstad model easier to work with as your manufacturer only needs to supply an RMS surface roughness value, which can be determined from a simple atomic force microscope (AFM) surface profile measurement.</p>

<p>In both models, the goal is to calculate K, which is then multiplied into R in the following lossy characteristic impedance equation:</p>
<img alt="PCB transmission line with a copper foil roughness correction factor" data-align="center" data-caption="&lt;em&gt;Characteristic transmission line impedance with a copper foil roughness correction factor K.&lt;/em&gt;" data-entity-type="file" data-entity-uuid="fac4e9f1-1992-45de-84cd-35d2c8f64136" data-responsive-image-style="" src="/sites/default/files/inline-images/copper-rough-1_0.png">
<p>The table below shows the formulas used to calculate K in the above equation.</p>
<img alt="Copper foil roughness and impedance in a PCB transmission line" data-align="center" data-caption="&lt;em&gt;Roughness correction factor equations.&lt;/em&gt;" data-entity-type="file" data-entity-uuid="3cffd942-1dd8-4111-a3ef-35e73744f1ba" data-responsive-image-style="" src="/sites/default/files/inline-images/t-line-rough2.png">
<p>I’d like to point designers to a <a href="https://www.signalintegrityjournal.com/ext/resources/article-images-201… 2018 paper</a> for more information on using a related set of formulas for causal copper foil roughness correction factors. Notice that the copper foil roughness correction factors above are functions of frequency, so you will need to choose a limiting frequency value (usually 10 GHz is a good benchmark). Once you’ve calculated this value, you can enter it into the impedance profiler in Altium Designer.</p>

<h2><a id="including-causal-copper-foil-roughness-in-altium-designer">Including Causal Copper Foil Roughness in Altium Designer</a></h2>

<p>Copper foil roughness is quite easy to include in the layer stack manager in Altium Designer. Once you’ve created a blank PCB and you are designing your stackup, simply click on the Impedance tab at the bottom of the layer stack manager. This will bring up the Impedance Profile window, as shown below. In this window, you can input the copper foil roughness parameters for your board, and the electromagnetic field solver will automatically determine the geometry that meets your target impedance within your desired tolerance.</p>
<img alt="Modeling copper foil surface roughness and a roughness factor in Altium Designer" data-align="center" data-caption="&lt;em&gt;Example impedance profile calculation in Altium&amp;nbsp;Designer (see lower right for copper roughness parameters).&lt;/em&gt;" data-entity-type="file" data-entity-uuid="c68f6dfe-0d65-4e17-b9a1-39bd1a62cd85" data-responsive-image-style="" src="/sites/default/files/inline-images/diff-pair1A.png">
<p>The impedance profiler will automatically calculate the interconnect impedance for your layer stack and the roughness parameters you entered. You can then save this impedance profile and use it in your design rules using a net-specific or net-class specific custom query. This helps you semi-automate tasks like l<a href="https://resources.altium.com/p/delay-tuning-for-high-speed-signals-what… tuning/delay tuning</a>, <a href="https://resources.altium.com/p/routing-differential-pairs-altium-design… pair routing</a>, and <a href="https://resources.altium.com/p/basics-signal-integrity-analysis-your-pc… integrity calculations.</a></p>

<h2><a id="a-note-on-accuracy">A Note on Accuracy</a></h2>

<p>The more mathematically minded designer will look at the above equations and note that there is significant variation in impedance with frequency. Because defined impedance values are most often used in high-speed digital PCBs, the transmission lines used on these interfaces are most often differential and the interfaces require high channel bandwidths.</p>

<p>Because of the variance over frequency, and the fact that today's EDA tools are only powerful enough to use a single impedance value as a constraint in PCB routing rules, it is appropriate to question how well the enforced routing rules will ensure channel compliance up to high frequencies. To ensure signal integrity over broad bandwidths, a designer should:</p>

<ul>
<li>Validate the impedance profiler value by simulating the completed routing in a post-layout simulator (like Simbeor or Ansys)</li>
<li>Test fabricated transmission lines on a test board, either in-house or by requesting controlled impedance testing from a manufacturer on a test coupon</li>
</ul>

<p>In my opinion, the best approach here is to use the Dk and Df values for your dielectrics that are at least equal to the upper limit on required channel bandwidth; normally this would be the <a href="https://resources.altium.com/p/whats-difference-between-data-rate-and-b… frequency</a> for the interface in question.</p>

<p>The takeaway is: the value you get the Altium Designer's impedance profiler (and every other PCB stackup-based impedance profiler) is a good estimate, but it does not capture all the information you would get in an S-parameter plot for your transmission line. In fact, because the impedance profiler is only calculating the parameters in a straight geometry, it will <em>never</em> capture all the information you would get from testing and post-layout electromagnetic simulations. At low channel bandwidths (up to a few GHz), this will not matter as much, but it becomes much more important at higher bandwidths.</p>

<p><a href="https://www.altium.com/altium-designer">Altium Designer®</a> contains many more layout and routing features for your next advanced design. Once you’ve incorporated copper foil roughness into your stackup, your impedance profile will be accessible by all the other design tools and your high-speed design rules. This is critical for ensuring your next advanced design meets important signaling standards and that interconnect losses are kept in check.</p>

<p>Now you can download a <a href="https://resources.altium.com/p/pcb-design-software-download">free trial</a> of Altium Designer and learn more about the industry’s best layout, simulation, and production planning tools. <a href="https://www.altium.com/contact-us">Talk to an Altium expert today</a> to learn more.</p>