How BGA Pin Pitch Impacts Signal Integrity at 224G-PAM4 and 448G

It seems like the PCB industry is always lagging behind semiconductor packaging, both in terms of manufacturing and signal integrity. As the industry looks forward to 224G interfaces moving from demo to production, the Ethernet Alliance and organizations like SNIA/SSF are focused on the next generation of ultra-high data rates. The major factors impacting signal integrity again change once you reach the 28 to 56 GHz bandwidth range, bringing more loss and signal distortion at the package-to-PCB interface.

The reason for this is not due to a change in the loss profile from dielectric to copper roughness. The reason is due to the structures of vertical transitions into the PCB, and particularly those on the bottom side of a BGA package. Via designs for BGA fanout routing are a major factor impacting signal integrity at 224G-PAM4 and the next-generation 448G data rates. As the industry looks ahead to these faster data rates, the factors determining signal integrity in packaging and PCB structures at 56 GHz will also apply at the higher channel bandwidths required in 448G.

As we will see below, the BGA and connector pin pitch and size that worked at 56G-NRZ and 112G-PAM might not work at 224G-PAM4, and will definitely not work at 448G. We will look at how these structures impact signal integrity and the important metrics that must be used to evaluate MIA and ball-out transitions into the PCB and within packaging.

Why Does BGA Pitch Matter for Signal Integrity at 224G PAM4?

224G PAM4 interfaces have a Nyquist frequency of 56 GHz, and this requires channel bandwidth span from DC to at least this value. Near 56 GHz, the typical ball and via structures connecting to BGA packages in PCBs have size and length scales that nearly match electromagnetic field resonances. When these resonances are reached, we start to see severe bandwidth limiting effects. And because those resonances are functions of the pin pitch, we now must consider this as part of package design when working at these frequencies.

• Designing vias to have accurate input impedance matching all the way up to 56 GHz is a related challenge. It is related because of the following:
• Differential interfaces operating at 56 GHz bandwidth require matched input impedance throughout the bandwidth specification
• Vias can start to radiate due to lack of electromagnetic field localization below 56 GHz
• Stitching vias are then needed to restore localization of the electromagnetic field around the signal vias
• The differential via antipad and layer thicknesses influence via input impedance in different frequency ranges
• Ensuring better input impedance matching and localization at or beyond 56 GHz requires smaller distance to antipads

Why 56 GHz Is the Magic Frequency

Channel bandwidth becomes limited by BGA pin pitch because the pin pitch is involved in determining the non-TEM mode frequencies in a via structure. This applies to the vias passing through the IC substrate and into the PCB. When the limit on TEM mode propagation is hit, there is a brick-wall impedance discontinuity at that frequency. This determines the channel bandwidth limit in the TEM mode. This is well known to occur in lasers and fiber optics, and we will now have to deal with this in PCBs as well.

Let's look at a typical ball and via structure coming from a 224G PAM4/448G package into a PCB as shown below. If you take a look at my previous articles on stitching vias and antipads for setting via impedance, you will find that the stitching vias impact localization, and the distance to stitching vias around differential vias for 224G PAM4 and 448G lanes is equal to the BGA pitch.

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This geometry creates a differential coaxial waveguide around each transmit and receive differential pair on the package ball-out. The size and spacing of copper elements in the package, PCB, and footprint will determine several important signal integrity metrics:

• TEM mode cutoff frequency
• Group delay dispersion within the via transition
• Differential via-to-via crosstalk
• Localization of the electromagnetic field
• Return loss looking into the PCB

If we zoom into one of the differential via pairs, we can roughly estimate the first non-TEM mode resonant frequency simply by looking at the geometry of the structure and using an effective Dk value. This calculation is based on the ball pitch p.

We can calculate the first non-TEM resonant frequency corresponding to a half-wavelength value inside a via transition on the bottom of the BGA package:

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Assuming a BGA with pitch = 1 mm and an effective Dk = 3 for a standard low-Dk PCB laminate, the first non-TEM frequency would appear at:

That is surprisingly close to the minimum required bandwidth for 224G PAM4 interfaces, so we should be suspicious that 1 mm pitch will limit the bandwidth due to non-TEM mode excitation and a resulting brick wall impedance discontinuity. 1 mm ball pitch will definitely not work for a 448G channel unless the 448G per lane standard implements an interface with very low baud rate.

If instead we use a ball pitch of 0.8 mm, then the maximum possible bandwidth for quasi-TEM mode propagation is roughly estimated to be:

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Just from this fundamental estimate, it should be clear to anyone with a basic knowledge of electromagnetic waves and resonances that the pin pitch is a potential major bandwidth limiter. As we’ll see in the coming sections, as we get to higher data rates, the required channel bandwidth increases, and this will require smaller pin pitch.

How BGA Pin Pitch Limits Channel Bandwidth

Data in the graphs shown below is provided by Intel as part of the IEEE 802.3 Working Group.

TEM Cutoff Frequency

The physical mechanism by which BGA pin pitch limits Channel bandwidth is described above. The graph below shows some raw data for a BGA package on a PCB built with megtron laminates. From this graph, we can see clearly that the pin pitch has a major effect on the available channel bandwidth by setting the TEM mode cutoff.

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TEM mode propagation limits for BGA pitch values on Megtron substrate materials.

Note that the TEM cutoff for the 1 mm ball pitch and 0.8 mm ball pitch are 58 GHz and 72 GHz respectively, both of which are shockingly close to my estimates given above…

Right at the TEM cutoff frequency, there is a very strong impedance discontinuity as the electromagnetic field propagation mode switches to a higher order mode. The strong reflection near the TEM cutoff frequency creates a corresponding drop in the differential insertion loss.

Insertion loss in the quasi-TEM mode as a function of ball pitch and pad.

In both cases, Here we would need to select a ball pitch that pushes this TEM cutoff frequency to a higher value, and we must design the vias so that the input impedance looking through the vias matches the required target impedance of the channel. For 224G-PAM4 lanes, this requires mostly flat impedance up to the Nyquist frequency of 56 GHz with less than -10 dB or -15 dB return loss.

Group Delay

Another important factor that describes signal integrity in wide bandwidth channels is group delay. Essentially, group delay describes the propagation velocity of each frequency component that makes up a signal travelling in a channel. Ideally, we want to have all frequency components to have the same group delay. When group delay dispersion is too large, different frequency components are travelling at different rates and the edge rate will appear to degrade (slow down). This can happen even in a (theoretical) channel with zero insertion loss.

In the graph below, we can see variation in the group delay for the shown ball structure considered above. In all cases, the group delay shows an increase as the TEM limit is neared and eventually breached. Smaller ball pitch pushes this upswing to higher frequencies and ensures low dispersion over a broader bandwidth.

Why is group delay important? It is because channels that create larger variation in group delay will create more distortion in a propagating signal. While a direct measurement of an eye diagram does not directly tell you the group delay, a lot of distortion or stretching of signals in an eye diagram is an indicator of large group delay dispersion.

Vias Are the Challenge at 224G and Higher Data Rates

At a recent 448G Ethernet Symposium event, there were two items up for debate:

• What pulse amplitude modulation format will be used at 448G per lane data rates?
• Can traditional interconnect structures with cables, traces, and vias provide enough channel bandwidth with these data rates?
• Based on the amplitude modulation used, will routing through PCBs at these data rates be possible?

Currently, at 224G-PAM4 data rates, it is doubtful whether PCBs will enable routing very far outside of the package, such as to a connector for a transceiver module. This has recently brought up the topic of near-chip or in-package connectors, which forces placement of the transceiver modules very close to the processor package in order to limit total insertion loss.

In order to successfully route 448G signals into the PCB, several tasks have to be completed successfully, both in the package and in the PCB:

• The BGA pin pitch must be small enough to handle the channel bandwidth at 448G
• Vias from the BGA into the PCB must be designed with matching to the input impedance
• Signal vias in the vertical transition into the PCB require stitching vias for localization
• The BGA package requires interleaved ground vias to prevent via-to-via crosstalk

If these tasks are completed successfully, it is possible to get signals into the PCB from a package at 224G and 448G. Whether those signals can be routed any appreciable distance without bumping up signal levels or requiring a new equalization scheme is another question entirely. For now, it should be clear from the above list that the BGA pitch will be a big determinant of signal integrity, and it will determine how you design signal vias for 448G channels and build the PCB stack-up in order to complete BGA fan-out routing.

It Only Gets Tougher at 448G

As of 2024, Ethernet standards groups (802.3 working group, Ethernet Alliance, and SNIA) still have not agreed on which modulation format will be used for 448G per lane data transmission. The two PAM formats being actively discussed are PAM6 and PAM8. PAM6 is easier from an interface IP design perspective and gives a minimum required channel bandwidth of 86.7 GHz. PAM8 is easier from a PCB and package design perspective and gives a minimum required channel bandwidth of 74.7 GHz.

Regardless of the modulation used, the BGA pin pitch will have a major effect on the channel bandwidth in the systems. Eventually, this pushes designs into the regime where it may be desirable to bypass the IC substrate-PCB interface altogether and build everything with the 448G interfaces as substrate-like PCBs. This would be a much more expensive type of build, even when built as small modules mounted on traditionally built rigid PCBs. It remains to be seen what approach the industry will take to build these more advanced products.

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