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The Basics of Signal Integrity Analysis in Your PCB

Zachariah Peterson
|  Created: September 21, 2020  |  Updated: August 28, 2022
The Basics of Signal Integrity Analysis in Your PCB

The basics of signal integrity analysis in your PCB can be anything but basic. Signal integrity simulation tools are great for calculating the behavior of signals in different nets during schematic and layout design, but you’ll still need to take some steps to interpret the results. As advanced as some signal integrity and EM simulation tools can get, they simply can’t compare to the information you can glean from measurements. Whichever method you use to examine signal integrity in your board (you should do both), there are some important steps you can take to analyze the behavior of your signals and identify problems in your board.

Getting Started with Signal Integrity Analysis

Signal integrity analysis begins with simulations at the pre-layout phase. Once you build up your layout, you can use some important post-layout simulations to analyze geometry-dependent signal integrity in your board. At some point, you will need to compare your signal integrity simulation results with real measurements, so keep your results handy for comparison.

Pre-Layout Analyses

This portion is really about circuit design, component selection, and examining how signals travel between I/Os on two components. There are three important analyses that tell you a significant amount of information about your board’s behavior.

S-parameters and transfer functions in signal integrity analysis
Relationship between S-parameters and a transfer function for a 2-port network.

In more complex channels, the above set of pre-layout analyses can help you qualify things like planned via transitions, 

As long as you know the structure of each of these elements before you create the design, you can

Post-Layout Analyses

This portion is really about examining how parasitics in your board affect signal integrity. As parasitic signal integrity effects are functions of board geometry, you’ll need to examine the following geometry-dependent signal integrity problems:

Tools for Signal Integrity Analysis

The above points might as if you need a complex simulator program to build and run these signal integrity analysis tools. The exact tools you need will depend on what you want to simulate and evalutate. Inside your EDA tool, some of these simulations are simply done with something like IBIS, while more complex simulations with multiple nets can require a 3D field solver or a comparable 2D solver tool.

Single-ended Buses With No Impedance Spec

In slower single-ended buses without termination, it is possible to observe some transient behavior (ringing) that could be due to the structure of the interconnect (its capacitance and inductance). This is something that could be observed in SPI when the trace is electrically short. In these buses, it is possible to observe ringing pre-layout as long as you have a transmission line model applied in your schematics and as long as the pin specification is defined (either SPICE subcircuit or IBIS model).

Lossless transmission line schematic
Example lossless transmission line model in a schematic.

When the single-ended bus is actually routed, you can run a post-layout simulation with the signal integrity analyzer in your EDA tools. These analyzers can use either a logic family assignment or an IBIS model for the relevant pins/nets to simulate:

  • Crosstalk waveforms, and to identify strong coupling regions
  • Reflection waveforms
  • Other signal behavior metrics (rise/fall time, overshoot/undershoot, etc.)
  • Calculate average impedance along the length of the track

In single-ended buses without an impedance specification, it is possible to observe reflections at the driver end when the bus gets long, or ringing due to the capacitance and inductance on the bus. If ringing produces excessive overshoot, then reducing the trace inductance and adding damping are the two main paths forward in reducing the ringing amplitude. The other is to increase damping by adding a series resistor, something which you would do with a low-impedance buffer output into a longer mismatched transmission line.

Impedance Controlled Buses

In single-ended and differential impedance-controlled buses, the terminating impedance could be on-die, so a logic family-based simulation in post-layout is not effective as it does not correctly describe the impedance of the bus. Crosstalk can still be simulated because you are only looking at coupling between two interconnects as a function of rise time, and the crosstalk magnitude will inversely scale with rise time accordingly, even if you only assign a logic family.

In the case of a post-layout simulation for reflections and impedance violations, a simulation in this case should at least use IBIS models to define buffer behavior rather than relying on logic family descriptions. As long as the buffer description is known and available, it can be applied to model the behavior of the component in the PCB Editor. The standard signal integrity tool in a PCB editor for crosstalk and reflection waveforms can help with a lot of up-front qualification of signal behavior (rise/fall time, overshoot, crosstalk, consistent impedance, and ringing) before moving into a more advanced analysis tool.

Signal integrity simulation ringing
Exaple reflection and crosstalk data in a routed net. The top result (reflection) depends on the specific logic family and may not always be accurate unless a validated IBIS model is applied. The bottom result (crosstalk on a victim net) depends on the rate of voltage change and is independent of logic family.

To simulate things like eye diagrams, multi-net crosstalk, and impedance deviations along the length of a net, there are external tools that can be used. Field solvers are one option, and there are many of these tools available with different levels of specialization. Something like a full-wave field solver is not always necessary unless you want to simulate radiated emissions, something deeper with SI/PI, or extract S-parameters in the simulated net.

The powerful PCB design and analysis tools in Altium Designer® give you a useful starting point for signal integrity analysis with pre-layout and post-layout signal integrity simulation tools. These accurate calculations give you a baseline for comparing your measurements. You’ll also have access to a complete set of manufacturing planning and documentation features in a single platform.

Now you can download a free trial of Altium Designer and learn more about the industry’s best layout, signal integrity simulation, and production planning tools. Talk to an Altium expert today to learn more about Altium Designer.

About Author

About Author

Zachariah Peterson has an extensive technical background in academia and industry. He currently provides research, design, and marketing services to companies in the electronics industry. Prior to working in the PCB industry, he taught at Portland State University and conducted research on random laser theory, materials, and stability. His background in scientific research spans topics in nanoparticle lasers, electronic and optoelectronic semiconductor devices, environmental sensors, and stochastics. His work has been published in over a dozen peer-reviewed journals and conference proceedings, and he has written 2500+ technical articles on PCB design for a number of companies. He is a member of IEEE Photonics Society, IEEE Electronics Packaging Society, American Physical Society, and the Printed Circuit Engineering Association (PCEA). He previously served as a voting member on the INCITS Quantum Computing Technical Advisory Committee working on technical standards for quantum electronics, and he currently serves on the IEEE P3186 Working Group focused on Port Interface Representing Photonic Signals Using SPICE-class Circuit Simulators.

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