The Basics of Signal Integrity Analysis in Your PCB

Zachariah Peterson
|  Created: September 21, 2020  |  Updated: September 25, 2020
The Basics of Signal Integrity Analysis in Your PCB

The basics of signal integrity analysis in your PCB can be anything but basic. Signal integrity simulation tools are great for calculating the behavior of signals in different nets during schematic and layout design, but you’ll still need to take some steps to interpret the results. As advanced as some signal integrity and EM simulation tools can get, they simply can’t compare to the information you can glean from measurements. Whichever method you use to examine signal integrity in your board (you should do both), there are some important steps you can take to analyze the behavior of your signals and identify problems in your board.

Getting Started with Signal Integrity Analysis

Signal integrity analysis begins with simulations at the pre-layout phase. Once you build up your layout, you can use some important post-layout simulations to analyze geometry-dependent signal integrity in your board. At some point, you will need to compare your signal integrity simulation results with real measurements, so keep your results handy for comparison.

Pre-Layout Analyses

This portion is really about circuit design and component selection. There are three important analyses that tell you a significant amount of information about your board’s behavior.

S-parameters and transfer functions in signal integrity analysis
Relationship between S-parameters and a transfer function for a 2-port network.

Post-Layout Analyses

This portion is really about examining how parasitics in your board affect signal integrity. As parasitic signal integrity effects are functions of board geometry, you’ll need to examine the following geometry-dependent signal integrity problems:

The exact steps you should take depend on what exactly failed. Strong reflections can result from minor impedance mismatches, producing a stair-step response in digital signals, thus your impedance mismatch must be reduced (ideally, it should be zero). Ringing results from parasitic inductance and capacitance. If ringing produces excessive overshoot, then reducing parasitic inductance and capacitance by the same factor will keep your trace characteristic impedance constant while increasing damping in the circuit, which will reduce the ringing amplitude. The other is to increase damping by adding a series resistor.

Eye Diagrams in Signal Integrity Analysis

One of the most fundamental measurements used in digital systems, particularly in Gigabit networking equipment and amplitude modulated signaling, are eye diagram measurements. Simulating bit error rates in a digital channel requires accounting for noise sources in your board, which are not always known a priori. This particular measurement helps you quantify a wealth of information from a single measurement. You can extract the following information directly from an eye diagram measurement:

If we assume that multiple noise sources in the circuit are uncorrelated (i.e., independent), and that each noise source has zero autocorrelation (this is the case for Johnson-Nyquist noise and 1/f noise), then any averages of our measurements from an eye diagram will converge to a Gaussian distribution. This means we can extract the average signal levels and timing jitter using some basic statistical analysis. If you are working with multilevel signaling, you can apply the average signal level measurements at each level. There are some other measurements you can extract from your eye diagram; take a look at this support article from Keysight for guidance on other measurements.

Using an eye diagram for signal integrity analysis
Eye diagram and statistics for the 0 level. This image was adapted from the eye diagram in Jason Ellison’s recent article on COM.

From here, we can quantify the bit error rate by counting the number of times the signal level falls outside the required noise margin. Since you are normally working with billions of bits, it is easier to calculate the cumulative probability that the signal level reaches the threshold for the undefined region for each signaling level. Since we are generally working with a Gaussian distribution (see the histogram above), the probability that the signal reaches the undefined upper or lower threshold can be calculated easily using error functions. There are plenty of open source programs and online calculators that will calculate this cumulative probability for you quite easily.

When comparing the real bit error rate to the required bit error rate, you can determine whether or not you need a forward error correction technique. With multilevel signaling, you can also determine whether you need some equalization scheme. Dynamic feedback equalization is one scheme that is already useful for 400G with PAM-4, although other equalization schemes are better for reducing ISI in different situations.

The powerful PCB design and analysis tools in Altium Designer® give you a useful starting point for signal integrity analysis with pre-layout and post-layout signal integrity simulation tools. These accurate calculations give you a baseline for comparing your measurements. You’ll also have access to a complete set of manufacturing planning and documentation features in a single platform.

Now you can download a free trial of Altium Designer and learn more about the industry’s best layout, signal integrity simulation, and production planning tools. Talk to an Altium expert today to learn more about Altium signal integrity.

About Author

About Author

Zachariah Peterson has an extensive technical background in academia and industry. He currently provides research, design, and marketing services to companies in the electronics industry. Prior to working in the PCB industry, he taught at Portland State University and conducted research on random laser theory, materials, and stability. His background in scientific research spans topics in nanoparticle lasers, electronic and optoelectronic semiconductor devices, environmental sensors, and stochastics. His work has been published in over a dozen peer-reviewed journals and conference proceedings, and he has written 1000+ technical blogs on PCB design for a number of companies. He is a member of IEEE Photonics Society, IEEE Electronics Packaging Society, American Physical Society, and the Printed Circuit Engineering Association (PCEA), and he previously served on the INCITS Quantum Computing Technical Advisory Committee.

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