Design Phase – Lid Assembly Electronics Part 2

Welcome back to the Open Source Laptop Project series! So far, we’ve discussed the functionality and component selection of the lid assembly electronics, we’ve taken a closer look at the schematic capture, and we’ve prepared the project for the PCB layout design.

In this update, we’ll tackle the PCB design of the webcam board with some expected challenges ahead; e.g., dealing with the overall small form factor of the board or breaking out the microscopic webcam image sensor.

Image Sensor Package

Let’s start by taking a closer look at the webcam image sensor and matching footprint. The image sensor OV2740 is available in several packages, image sensors are often sold as a bare die that is either glued or soldered directly onto the PCB. The sensor is then bonded to the board using thin gold bonding wires to break out all the necessary signals.

OV2740 die bonded to a PCB

There are several reasons for using a bare die instead of a fully packaged sensor. The three most prominent reasons are cost, form factor, and optical properties. First, let's consider the cost: packaging an image sensor without impacting the optical performance is an expensive process. Bonding the sensor die without a package directly to the PCB saves the packaging cost, but comes at a higher assembly/manufacturing cost. Bonding optical components on a PCB usually requires a clean-room setup as well as a bondable PCB surface finish. Both options drive up the manufacturing cost, which is why direct die attach is usually only viable for high volume or highly specialized products.

Another good reason to choose the direct die attach method is to decrease overall solution height, especially with densely integrated camera solutions for laptops or smartphones, where every fraction of a millimeter in the Z-axis counts. If the image sensor's active die is elevated 0.5mm above the board surface, the extra height must be compensated by the lens assembly. This often results in an increased thickness of the whole image sensor and lens stack.

Moreover, the ease of mounting the lens assembly serves as yet another compelling reason for utilizing the bare sensor die. The sensor die must be perfectly perpendicular to the lens assembly axis in order to achieve an undistorted image. The lens assembly is mechanically referenced to the PCB surface which must be perfectly parallel to the image sensor die. If the image sensor is packaged as a BGA component, for example, it is difficult to guarantee it will be perfectly parallel to the board surface. This effect needs to be compensated by the lens assembly, but is usually not present with the direct die attach approach.

For our laptop design, attaching the sensor die directly to the PCB surface is not an option due to increased manufacturing cost. Therefore, we will use the OV2740 packaged as a fine pitch BGA component.

OV2740 image sensor in a BGA package

Image Sensor Footprint

The sensor package is not a regular BGA package, but instead a multi-pitch grid array. In our case, this means the solder balls have a different pitch in the X- and Y-axis:

BGA footprint of the image sensor

The screenshot shows that the BGA footprint uses 0.53mm pitch in the X-axis and 0.48mm in the Y axis. This comes with some implications for the PCB design and manufacturing technology we have to choose for the board. Most PCB providers can manufacture a 0.1mm trace width and spacing in the standard process. If we'd like to choose standard design rules without paying additional costs for a higher technology class we can only break out the sensor pins in the Y-axis:

BGA component breakout

Since the pin-pitch in the X-axis is slightly larger, we can conveniently fit a 0.1mm trace in between two pads. If we would like to also break out the second row in the X-axis, we would need to choose 0.09mm trace spacing, which most manufacturers can’t handle with their default design rules.

The image sensor has five rows and we can break out the two outermost rows of pins without any problems. There is one row left in the middle that we can´t reach from the top layer. Placing a VIA with a 0.4mm pad and 0.2mm drill—the limits of most standard PCB design rules—between the pads is not an option because there wouldn’t be enough spacing from the VIA to the pads:

BGA footprint with VIAs

At this point, we can use one additional step in the PCB manufacturing process and that is plugging and capping the VIAs. By using capped VIAs we can place the VIAs directly in the pad without causing any reliability issues during the PCB assembly.

This way, the escape routing for the image sensor could look like the following:

Image sensor escape routing

Component Placement

With the PCB technology defined and armed with a fanout strategy we can now go ahead and work on the component placement on the board. Most of the component positions are already defined by the CAD model. The LEDs for the backlit touch icons as well as the sensing electrodes must be positioned underneath the matching cutouts in the coverglass. The position of the board-to-board connector that connects the webcam board to the mainboard is also predefined. We can import the placement information by importing the coverglass outline as a .DXF file onto the 3D body mechanical layer in Altium Designer. We can use these outlines as an anchor point and snap the components to the correct locations:

Imported DXF outline

The remaining component placement is driven by the schematic. The three voltage regulators needed for the image sensor are placed directly besides the keepout zone for the lens assembly:

Image sensor and voltage regulators

Each LED must be placed underneath a custom diffuser to guarantee a homogenous backlighting for the touch key icons. The diffusers are used for registration holes.

LED position relative to the diffuser registration holes

With the component placement done, we can get a good impression of the routing density we are dealing with and select a suitable layer stack based on this information. For the webcam PCB, we will be using a six-layer board with impedance control on the top and bottom layer. We won't be routing any impedance controlled traces on the bottom layer, but the impedance control is usually only offered as a mirror symmetric option in the layer stack. The image sensor uses a two-lane MIPI CSI-2 interface to transmit the image data to the ISP. The CSI-2 interface needs to be routed with 100 Ohm differential impedance.

PCB Layout

In the first step of the PCB layout we will take care of routing the image sensor and connecting it with the board-to-board connector. The decoupling capacitors were placed close to the image sensor on the top layer as no components are allowed on the bottom layer of the board. We want to use short and wide traces to connect the capacitors to the sensor. The LDOs close to the sensor are connected using solid copper regions to provide a little extra thermal spread. In the middle of each LDO pad a GND VIA was placed to spread the heat into the GND planes of the board.

The routing of the image sensor and power supply section looks like this:

Image Sensor routing

The three differential pairs leaving the two top rows of the image sensors are the MIPI CSI-2 interface. We would like to make sure that the signal edges in each complimentary trace within the differential pair propagate in parallel/at the same height along the traces.

Due to the way the CSI-2 signals are leaving the footprint, a small delay is introduced close to the component. We can counteract this delay by adding our Intra-Pair length tuning primitives near the BGA pads.

Intra-Pair length tuning close to BGA pad

The LEDs were connected by using a solid region for each LED pad. This provides some extra thermal spreading and therefore better cooling of the LEDs. Since we are not using high-power LEDs the thermal performance is not critical in this case though.

LED connection using solid regions

Finally, the inner layers are used for a solid ground plane on inner layer 1 and inner layer 4, and power is routed on inner layer 2 and 3:

Power routing on inner layer 3

There are a few sections with little copper area left in the power planes which could cause excessive IR drop. Fortunately, the whole board draws only 25mA during normal operation with no current spikes so the losses within the copper geometry will be negligible.

You can take a look at the finished PCB design here:

With the PCB design done, we can order the first prototypes of the webcam board and start testing the system! This brings us one step closer to finishing the lid assembly milestone. Once the webcam board testing is done, we can focus on connecting the whole lid assembly to the rest of the system. We just have to figure out a FPC design for transmitting image sensor data to the mainboard. A second FPC will be needed to connect the mainboard to the eDP display in the screen assembly.

These topics and more will be covered throughout the Open Source Laptop Project. Stay tuned to find out which signal integrity challenges await during the FPC design!