PCB Design For Test Structures And Tests Performed, Part 2

In Part 1 of my article I outlined the various test structures that can and should be incorporated into any given PCB design. Included in this was a description of how they are built, where they are located and how they are used to ensure PCB structural and performance integrity. As speeds have increased and designs have become much more complex, test structures have become a necessity rather than features that can be added indiscriminately. And, as noted previously, there are three places in the manufacturing process where testing is necessary. 

These include:

• Bare board test. The two places where board test occurs:
  • Receiving inspection by the OEM or the contract assembler.
  • At the fabricator’s facility.
• Assembled board test.
• Repair center test.

I will discuss the foregoing in order.

Bare Board Tests

Tests performed at the PCB fabricator’s facility include:

• Connectivity tests.
• Impedance tests.

Connectivity testing is done with a tester that compares the way the finished PCB is connected to the generated net list that serves as the standard. The net list against which the PCB is compared can either come from the CAD system used to design the PCB or from the fabricator’s CAM (computer aided manufacturing) station that generates the net list. The first is often referred to as the CAD net list and the latter as the CAM or Gerber net list.

Testing to the CAD net list is always preferred as it guarantees that the PCB matches the schematic. (An important step in generating the PCB manufacturing data at the fabricator is to extract a net list from the Gerber data and compare it the CAD net list to make sure they match. This is the way to ensure no errors have crept into the Gerber data that will be used to fabricate the PCB). The most common form of CAD net list is IPC-D-356. All PCB design systems are capable of generating such a net list. This net list is different than the CAD net list used by design engineers. The net list used for testing has the physical location of the points in each net attached to it. This information is used by the fabricator to locate the pins in each net as well as to build the test fixtures. 

Testing a bare PCB for proper connectivity can be accomplished through either a bed of nails tester or a flying probe tester. Figure 1 is a typical bed of nails test fixture. This is a double-sided test fixture that makes contact with test points on both sides of the tested PCB. Shown are two frames in which long spring loaded needles are mounted. Each needle contacts a test point on the PCB under test at one end, and a pin electronics circuit in the tester at the other. These two halves are inserted into a tester, one to contact the top of the PCB and the other contact to the bottom.

Figure 1. A Bed of Nails Bare PCB Test Fixture

The advantage of bed of nails testing is that there is a very low test cost per PCB. The disadvantage is the cost and lead time of building each test fixture. Bare PCB testing rarely needs any test points added as contact is made with the component mounting pads.

Figure 2 is a photo of a flying probe tester. With this type of testing, there is no need to build a test fixture. The PCB is mounted into the tester and probes then move around to contact the points in each net. These points are located using the CAD net list. The advantage of this test method is that no test fixture is required. This makes it ideal for very small quantity testing and it eliminates the time and cost of a test fixture. It is also valuable for PCBs that have component lead spacing that is too close to allow the use of a bed of nails tester. The disadvantage of this test method is that is takes longer to test each PCB than bed of nails testing. 

Figure 2. A Flying Probe Bare PCB Tester

Impedance testing can be done either at the fabricator or at the OEM. This testing is done to make sure the transmission lineimpedances in each signal layer are correct. This is done using an instrument known as a Time Domain Reflectometer (TDR). Figure 3 is a typical impedance test setup at a PCB fabricator.

Figure 3. An Impedance Test Station at a PCB Fabricator

The tester shown is manufactured by Polar Instruments of Hampshire England. It is designed as a production instrument and has data logging capability. It is the most common impedance tester used by PCB fabricators. 

Figure 4 is an impedance test setup using a Tektronix 1502C time domain reflectometer. This instrument, or one like it, is likely to be used at the receiving inspection station or at an OEM.

Figure 4. A Tektronix 1502C Time Domain Reflectometer Setup for Measuring Impedance

In order to perform impedance tests, it is necessary to design a test trace into each signal layer. There are two places where test traces can be located. In the first instance, the fabricator adds a special test coupon to each PCB or panel on which the PCBs are built. By using a standard test coupon it is possible to build test fixturing at a test station such as that shown in Figure 3. This simplifies the production test of controlled impedance PCBs. However, as noted in Part 1 of this article, there are two problems with this approach:

• The test coupon is rarely attached to the PCB to which it belongs, making traceability difficult and leaving the OEM with no test traces.
• There is no guarantee that the test traces in the coupon are the same width as those in the actual PCB.

We have witnessed instances where the trace widths in the test coupon are the correct width and those in the PCB are not. This results in building good test coupons and bad PCBs.

For the foregoing reasons, we recommend that impedance test traces be built into the body of the PCB itself. Using this methodology, you will know that the trace widths are correct and are always with the PCB, no matter where it goes. Also, as noted in Part 1 of this article, having small form factor PCBs does not negate the practice of building test traces into the PCB. It just takes a little imagination and some good engineering.

There is the potential that two impedance tests will yield different answers. This occurs because the measured impedance is influenced by the rise time of the time domain reflectometer that is used to do the testing. Table 1 shows the result of testing the same three traces with three different time domain reflectometers.

Table 1. Impedance Test Results Using Three Different time domain reflectometers

As can be seen, the impedance measured changed with the rise time of the test edge coming from the time domain reflectometer.

The results are as follows:

• The 40 pSEC edge came from an Agilent time domain reflectometer.
• The 125 pSEC came from a Tektronix 1502C time domain reflectometer.
• The 175 pSEC edge came from a Polar Instruments CITS800 production tester.

The difference between the Agilent and Polar measurements is approximately four percent. This is a large enough error to result in PCBs being rejected that are actually within specification. Since nearly all production testing done at a fabricator will use the Polar CITS800, it is imperative that all other entities making impedance measurements use the same instrument or adjust the time domain reflectometer rise time so that it is the same. 

The reason the impedance measurements differ is that the equivalent frequency content of each edge is different. The faster the edge, the higher the frequencies will be. The relative dielectric constant, εr, of nearly all PCB laminates goes down as frequency goes up. When the εr goes down, the impedance goes up. Therefore, a faster edge will result in a higher impedance measurement as is borne out in Table 1. The rise time used to test impedance should be the same as, or close to, the rise time of the signals traveling on the transmission line when the PCB is assembled. For most modern electronics this can be well below 50 pSec.

Where on a test trace impedance should be measured is another significant consideration. Figure 5 shows the screen of a time domain reflectometer that shows what resulted when the impedance of four different traces on the same PCB was measured. The vertical scale has been expanded to show variations in impedance along the length of a test trace as well as differences between test traces on different layers of the same PCB. The solid and dotted horizontal lines are the plus or minus 10% limits for this particular PCB with the center line being the nominal impedance. The transients at the left side of the display are impedance discontinuities associated with making contact with the trace under test. The sharp vertical lines at the right hand side of the display are the reflections off the open ends of the traces under test.

Figure 5. Impedance Test Display for a Series of 3” Test Lines

Notice that between these two events the traces gradually slope upward implying that the impedance rises along the length of the trace. However, this is not the case. This rise is the DC resistance along the length of the trace. Clearly, the results are affected by where along the trace the impedances are measured. For example, if the measurements were taken near the left end of the trace the value would be very close to 50 ohms. If the measurements were taken near the right end of the trace the values would be very close to 55 ohms. This results in a large enough difference to cause most boards in a PCB lot to be rejected.

The above plots and discussion raise a good question. Where along a trace should impedance be measured? In the case of some production testers, the average impedance along the length of the traces is reported. Is that the real impedance of the trace? Actually, it is the impedance plus some of the DC resistance along the length of the trace. (This is how the Polar Instruments tool reports impedance.) The correct method for measuring impedance is to measure as close to the start of the trace as possible to avoid skewing the answer with the DC resistance along the trace. To do this, the operator needs to position the cursor of the time domain reflectometer just after the transients related to connecting to the trace die out or as close to the left side of the display as possible. Reporting impedance plus DC resistance misleads the user. All of the analytical tools we use to model transmission lines take into account DC resistance of traces. In order to accurately correlate impedance tests with these modelers it is necessary to report impedance without including any of the DC resistance.

Bare Board Test at the OEM

As new PCBs arrive at receiving inspection at the OEM or contract assembler, some testing needs to take place to ensure the PCB meets specifications. Net list testing is too difficult to do at this point so the fabricator’s results must be accepted. The tests that can be performed at receiving inspection include:

• Impedance testing.
• Verifying that the stackup is correct.
• Measuring the amount of plane capacitance for each power supply voltage.

Impedance testing is performed as described above. Checking the stackup involves using a microscope to examine the stacking stripes added to the edge of the PCB for this purpose. These stacking stripes were discussed in Part 1 of this article.

Measuring the amount of plane capacitance is done with an ordinary capacitance meter connected between Vdd and ground of each supply voltage. It is also useful to add a pair of test contacts that are labeled on the silk screen to make them easy to locate. Again, this is described in detail in Part 1 of this article.

Assembled and Repair Center PCB Tests

Once a PCB has been assembled it is necessary to have a means to locate assembly defects such as solder shorts and opens as well as to perform functional testing. The usual method for locating assembly defects is with an in-circuit tester that is a bed of nails tester which makes contact with each net at only one place. The question is where this connection should be made. In most cases, it is made to a via on the bottom of the PCB which connects to the component lead on the other side of the PCB. Figure 6 is a bottom view of a BGA pattern showing the vias that will be contacted by the in-circuit tester pins. These pads are not covered by the solder mask.

Figure 6. Bottom View of a BGA Mounting Site Showing Exposed In-Circuit Test Points

For all nets that have at least one plated through hole or via allowing access to the net from the bottom of the PCB, no special test points are needed. The problem arises when a net is not accessible in this manner. The least expensive way to make contact with such a net is to add a via for the purpose of making it available at the bottom of the PCB. A good question is, where should this via be located and what affect will it have on the signal during normal operation? It has been shown that vias with drilled hole diameters of 12 mils or less will add approximately 0.3 pF of parasitic capacitance to the transmission line on which they are placed. It also has been shown that this additional parasitic capacitance has no adverse effect on signals as high as 5.2 GB/S. 

However, where this via is placed could cause signal degradation. If it is placed anywhere along the length of the net to which it is attached, there’s no problem. If a short trace is needed to route out from under a component to reach a bare place on the PCB surface, this short trace will act as a stub on the transmission line.

As discussed in the section on stubs of Volume 1 of our book, this can degrade the signal quality. Therefore, any short trace used to escape from under a component in order to allow access to a via must be done only at one end or the other of the trace.

On occasion, a small round pad is placed somewhere on a trace to allow access to a signal. These pads are typically 35-40 mils in diameter. We are often asked how this will impact a signal and, most importantly, if it will be detrimental. Such a pad will add a tiny amount of parasitic capacitance—much less than the via discussed above—and will do no harm unless it is located at the end of a trace segment that could create a stub.

Many modern designs have components on both sides of the PCB. In some cases, such as cell phones, the components are so densely packed that it is not possible to have vias that pass all the way though the PCB. This makes it impossible to use techniques such as in-circuit test in the assembly operation. Some special scheme must be designed into the circuits to allow test access to all of the nets on a PCB. This is usually accomplished using boundary scan or JTAG (Joint Test Action Group). Each IC has special circuits added to it that allow access to each pin through a special test scan bus. With this technique it is possible to access every signal pin on every IC to see if it can be moved between logic states and also to see if it is properly connected. Without JTAG, many newer designs would not be testable.

When a design has JTAG built into it, it is possible to exploit this feature to allow for designing the tests in such a way that field service personnel can use the same feature to perform failure analysis in the field or at a repair depot. This eliminates the need of having a manufacturing test suite along with a different field service test suite.

Summary

The process of designing test features and capabilities into a PCB needs to be addressed at the front end of the design process to ensure that test results across the fabrication, assembly, and repair center facilities are consistent with the actual operation of the PCB. Taking the time to design and build in the necessary test structures and factor in the correct test connection points can assure that the final board will work right the first time.

Have more questions? Call an expert at Altium or discover more about high-speed PCB Design with Altium Designer^®.

References:

1. Ritchey, Lee W. and Zasio, John J., “Right The First Time, A Practical Handbook on High-Speed PCB and System Design, Volumes 1 and 2.”

2. Ritchey, Lee W., “How Should Test Point Connections Be Connected To High Speed Nets?” Current Source Newsletter, Volume 2, Issue 1, Fall 2005.