PCB Trace and Pad Clearance: Low vs. High Voltage

Zachariah Peterson
|  Created: April 28, 2020  |  Updated: September 25, 2020
PCB Trace and Pad Clearance: Low vs. High Voltage

High voltage/high current designs carry safety requirements that need to be met by designers. Similarly, high-speed designs need to have suppressed crosstalk in order to ensure signal integrity. The key design aspects that relate to both areas are your PCB trace clearance and pad clearance values. These design choices are critical for balancing safety, noise suppression, and manufacturability.

The IPC 2221 voltage and spacing standards provide guidance for preventing ESD between conductors, but not all boards will need to meet this standard. Depending on thePCB trace distance voltage and frequency of your signals (or edge rate for digital signals), you may need a different value for your PCB trace clearance. Here’s how to balance these two aspects of your PCB clearance layout while also ensuring manufacturability.

Low Voltage (<15 V)

Under the IPC 2221 voltage and spacing standards, the minimum PCB clearance rules (really, the clearance between any two conductors) is 0.1 mm for general-purpose devices or 4 mils. For power conversion devices, this minimum PCB trace with and spacing is 0.13 mm, or 5.1 mils. These boards could hardly be considered “high voltage” and the conductor spacing in these boards starts to border on the HDI regime.

At these voltages, you may be working with digital signals, low-frequency analog signals, or simply DC at moderate current. With digital signals, the typical rule is to simply follow the “3W” rule, where the clearance between traces is triple the width of the trace. For a typical 50 Ohm controlled impedance microstrip, your trace width will be ~20 mils, thus the recommended PCB trace spacing is 60 mils. You’re still well within IPC 2221 requirements with these traces, and your primary focus should be efficient routing and DFM. Even in the HDI regime, where you may need to route between fine-pitch pads in a BGA, you won’t need to worry about these voltage requirements as you’re generally working at 3.3 V or ~1 V.

PCB trace clearance for thin conductors
When your routing is this tight, you’re still well within PCB voltage clearance requirements below 15 V. Instead, focus on signal integrity and DFM.

High Voltage (>15 V)

At high DC voltage, the primary concern in choosing a PCB trace clearance value is preventing ESD and dendritic growth between exposed conductors. With high AC voltage, or with a switching regulator that outputs high current, you now have to worry about crosstalk, as well as ESD and dendritic growth. Crosstalk suppression guidelines still over-specify the required PCB voltage clearance or spacing between conductors until you get to very high voltages.

To see how you might need to find a balance between IPC 2221 and crosstalk suppression, consider the following hypothetical situation. Suppose you have a controlled impedance microstrip (20 mil wide) near a high voltage AC line, or near traces running in/out of a high current DC regulator. If you follow the “3W” rule, the spacing between parallel microstrips and the nearby high voltage line should be 1.5 mm, or ~60 mils. This is more than enough to comply with IPC 2221 until the high voltage level reaches 180 V for power conversion devices or 340 V for other high-voltage products.

At high voltage, the concern is not so much a digital edge rate as is the frequency of a high voltage AC line. Any oscillating signal can induce a crosstalk signal in a nearby trace if the traces are close together; this is a known noise problem with high-voltage DC regulators and their downstream signal lines. At high output currents, such crosstalk can induce unintended switching in high-speed digital components. It’s best to opt for greater spacing between a high-voltage AC line and nearby DC or digital lines.


In general, we can define PCB trace spacing and pad clearance rules into three different regimes based on voltage. In the two lower rows, be sure to calculate the required PCB trace spacing using the IPC 2221 standard when determining which regime to work in. Note that, in the aforementioned article, your PCB trace spacing can be made smaller when your traces are coated or placed on inner layers.


Be sure to understand the difference between creepage and clearance in your design. Also, be sure to check that your traces will be wide enough to carry sufficient current without becoming too hot. This can be checked using the IPC 2152 nomograph.

Once you’ve figured out the best trace and pad clearances to use in your board, you need to encode these values as design rules in your ECAD software. The unified design engine in Altium Designer® allows you to define your required PCB clearance rules (both trace and pad) and values, and these design rules are instantly checked as you route your board. This makes Altium Designer the ideal application for low and high-voltage design tasks, as well as for high-speed and high-frequency designs.

Now, you can download a free trial of Altium Designer and learn more about the industry’s best layout, simulation, and production planning tools. Talk to an Altium expert today to learn more.

About Author

About Author

Zachariah Peterson has an extensive technical background in academia and industry. He currently provides research, design, and marketing services to companies in the electronics industry. Prior to working in the PCB industry, he taught at Portland State University and conducted research on random laser theory, materials, and stability. His background in scientific research spans topics in nanoparticle lasers, electronic and optoelectronic semiconductor devices, environmental sensors, and stochastics. His work has been published in over a dozen peer-reviewed journals and conference proceedings, and he has written 2500+ technical articles on PCB design for a number of companies. He is a member of IEEE Photonics Society, IEEE Electronics Packaging Society, American Physical Society, and the Printed Circuit Engineering Association (PCEA). He previously served as a voting member on the INCITS Quantum Computing Technical Advisory Committee working on technical standards for quantum electronics, and he currently serves on the IEEE P3186 Working Group focused on Port Interface Representing Photonic Signals Using SPICE-class Circuit Simulators.

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