SAP: PCB Reliability Beyond Test Results

Created: July 11, 2022
Updated: July 12, 2022
SAP:  PCB Reliability Beyond Test Results

As I am thinking about today’s blog, the phrase “Beauty is in the eye of the beholder” continues to run through my mind.  Specifically, in this context, there are many ways that the SAP processes that PCB fabricators are now offering can benefit PCB designers.  There is a body of work being done to understand how to utilize this new PCB manufacturing capability and each contributor has a slightly different version of what would be best.  That is logical given that everyone has different requirements for quality and reliability, different experiences of what works best for them, and different long-term requirements.

In a previous blog post, I shared quantifiable reliability data.  For some, this is the primary measure of reliability that provides confidence in this new approach and significant work has been done to build and test D-Coupons, IST coupons, SIR measurements and peel strengths.

For those not familiar with the semi-additive PCB process, please refer to a few of our previous blogs.  We have gone through the basics of SAP processing and recently looked at some of the top questions related to the printed circuit board stack up; explored some of the “design rules” or “design guidelines” that do not change when designing with these ultra-high-density feature sizes, and explored the design space around the possibility of utilizing these ultra-high-density circuit trace widths in the BGA escape regions and wider traces in the routing field.  The benefit is a reduction in circuit layers and the concern is maintaining 50-ohm impedance.  Eric Bogatin recently published a white paper analyzing just this benefit and concern. 

Circling back to my thoughts about “Beauty is in the eye of the beholder” in this blog I would like to explore options that are more qualitative than D-Coupon and IST testing yet are also intuitively options that will improve micro via reliability or reliability in general terms by making the printed circuit board easier to manufacture.  

As a starting point, I want to point out that the SAP processes are not developed or intended to solve all the fabrication complexities in today’s HDI printed circuit board designs.  If a fabricator struggles with laser drilling micro via’s, implementing an SAP process isn’t going to magically cure all fabrication challenges.

Semi-Additive Processes for PCB fabrication are developed to allow a fabricator to leap beyond the 75-micron (3 mils) trace and space barrier that is inherent in subtractive etch processing to trace and space feature sizes that go well below 25 microns (1 mil).  In fact, there are North American suppliers today that offer 15-micron lines and spaces.  

As a PCB Designer, what do you do with the space savings when you can now route with a 20- or 25-micron trace and space?    

Yes, in the paragraph above I mentioned the capability of a 15-micron line and space, but why push fabricators to their absolute limit as they navigate the learning curve of a new fabrication process?

Here are some of the more predominant application areas that I have seen.  I am sure there are many more and please feel free to share your thoughts!

  • Reducing line width can and will reduce layer count, which in turn reduces the number of micro via layers and the number of lamination cycles.
  • Reducing line width and space can free up real estate to use staggered micro vias rather than stacked micro vias.
  • Reducing line width can free space for larger thru-holes, potentially eliminating blind vias and allowing the designer to use thru-hole technology rather than stacked or staggered micro vias.

Let me share an example.  Because of the trace width and space constraint of 75 microns, printed circuit board design complexity often takes the path of adding layers, then blind via construction, adding staggered micro via layers, and then moving to stacked micro via layers.  A few things happen along this progression.  First, multiple lamination cycles are expensive, often a 40% cost adder per lamination cycle.  This is driven by the added cost to the PCB fabrication process itself and the added cost of reduced yields resulting from the added manufacturing complexity. This added complexity is also key in a PCB reliability discussion. 

In a specific redesign, the original design started as 12 layers with 3 levels of stacked micro vias.  Using 25-micron trace and space on selective layers, the layer count was reduced from 12 to 8, but potentially even more important, the design eliminated the need for multiple laminations.  That is a tremendous cost-saving, but also is arguably going to be a much more reliable PCB design.

This is a demonstrator redesign and not all designs will be able to have this dramatic result.  But, my challenge is to let your mind wander here for a bit.  Moving from 3 lamination cycles to 2 or even 1 added layer of micro vias is going to be a tremendous saving and improved reliability.  Moving from stacked micro vias to staggered micro vias has been shown time and again to improve micro via reliability and eliminating a blind via requirement and increasing hole size and pad size will improve both cost and reliability.  

Every PCB designer has many variables to balance based on their product needs, company requirements, and PCB fabricators capabilities.  Semi-Additive PCB processes offer a new tool in the toolbox and the opportunity for some more creative problem-solving to these complex PCB routing challenges.  What possibilities for improved reliability interest you the most?

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