SAP Reliability Data

Tara Dunn
|  Created: June 15, 2022  |  Updated: July 8, 2022
SAP Reliability Data

One of the questions I am regularly asked regarding Averatek’s A-SAP™ process is “what data do you have to demonstrate PCB reliability?”  This is an excellent question and an interesting blog topic.  I am going to share data specifically from printed circuit boards built with Averatek’s A-SAP™ process including D-Coupon, IST, and SIR results, and will also explore some less obvious ways to think about how SAP processes can improve the overall reliability of printed circuit boards.

For those not familiar with the semi-additive PCB process, please refer back to a few of our previous blogs.  We have gone through the basics of SAP processing, recently looked at some of the top questions related to the printed circuit board stack up, explored some of the “design rules” or “design guidelines” that do not change when designing with these ultra-high-density feature sizes. and explored the design space around the possibility of utilizing these ultra-high-density circuit trace widths in the BGA escape regions and wider traces in the routing field.  The benefit is a reduction in circuit layers and the concern is maintaining 50-ohm impedance.  Eric Bogatin recently published a white paper analyzing just this benefit and concern.  

Let’s start with the obvious reliability criteria:  D-Coupons, IST Coupons, peel strength testing, and SIR testing.  Ok, maybe SIR isn’t the most obvious criteria I could select, but because the A-SAP™ process utilizes a palladium-based catalyst system to achieve the ultra-thin layer of electroless copper, there were concerns about the palladium remaining conductive after processing, so I have included it here.

Surface Insulation Resistance Testing:

SAP Reliability Data

 

Any residual Palladium catalyst on the laminate surface does not become conductive and degrades the isolation between conductors.  Evidenced by comparable results between A-SAP™ and subtractive etch processing.

IST Testing:

Testing per IPC TM-650-26.26a
Plated Through Vias:

  • Passed testing at the 150oC test condition for 500 cycles

Micro via Circuits:

  • Passed testing at the 190oC test condition for 500 cycles following plated through via testing

D-Coupon Testing:  
Testing per IPC TM-650-2.6.27b Test Results

  • Multiple Licensees have tested multiple coupon configurations and the process runs on the OM Thermal Stress System with passing results.  Licensees include Calumet Electronics, American Standard Circuits, and FTG.  Additional test results were provided by NSWC Crane as the Executive Agent for Printed Circuits Boards for the Department of Defense.
  • Test conditions for Reflow Parameters were 6 cycles from 45 to either 230, 245, or 260oC followed by Thermal Shock Parameters of 100 cycles from -55 to 170oC.  
  • A total of 83 coupon sets from 6 different process runs were tested in the IPC TM-650-2.6.27b test with single vias, staggered vias, and stacked vias (2)
  • Additional tests are ongoing to increase process sampling and via stack depth which should be completed by the end of summer.

Peel Strength Testing:

There has been significant work performing peel strength testing on a variety of circuit board materials, including FR4, specialty materials, flexible circuit materials and build-up materials using the A-SAP™ process.  I hesitate to even include this because as soon as it is printed it is outdated with so much development work happening.  The list of circuit board materials below has all been tested with industry acceptable results for peel strengths.  Please don’t think that other materials do not pass testing, more likely, the testing just isn’t hasn’t been completed yet!

SAP Reliability Data

 

Calumet Electronics, the pioneer PCB fabricator that was the first to run the A-SAP™ process.  I asked Meredith LaBeau, Calumet Electronics CTO, where they are at with process development and she responded, “We have finished all the process development over the past two years, moving the manufacturing readiness level from a 5 to 9 (low-rate production).  Through this development process, we have done significant testing for reliability including peel strengths, thermal stress, and cycling with microvias, as well as staggered structures. Additionally, we have processed over 1000 panels, and tested them with electrical continuity and microsection analysis.

Through the development phases of A-SAP™, we have used the technology on all traditional and many non-traditional substrates, with success, as well as fabricating all traditional PCB features with passing reliability.”  

The data included here are specifically for the A-SAP™ process, currently being fabricated in the US.  A quick google search will also provide reliability data for the mSAP process being manufactured in high volume in Asia.  The mSAP process in Asia is being produced in custom-built facilities and is quite different than the mSAP processes being run in the US.  I have not personally seen any reliability data of this type for processes being run in US fabrication facilities.  

Thoughts on PCB reliability beyond test results:

Moving on from the traditional “reliability data” test information, I would like to also touch on some of the less intuitive ways that the SAP process can improve reliability.  For starters, microvia reliability has been an undisputed hot topic for many years with countless hours of work being done to understand the challenges and identify solutions.  Reducing the dependence on microvias, especially stacked microvias is certainly going to improve reliability.  SAP processes can help the printed circuit designer to do just that.  Reducing line widths from 75 microns and greater to 50 microns or less provides a few different benefits depending on what is important to each particular design:

  • Reducing line width can and will reduce layer count, which in turn reduces the number of micro via layers and the number of lamination cycles.
  • Reducing line width and space can free up real estate to use staggered microvias rather than stacked microvias.
  • Reducing line width can free space for larger thru-holes, potentially eliminating blind vias and allowing the designer to use thru-hole technology rather than stacked or staggered microvias.

In fact, each of these could be a case study in a future blog!  Please watch for our next blogs delving deeper into these benefits and exploring the benefits associated with the ability to use thinner dielectrics, maintaining impedance requirements while reducing the overall thickness of the PCB.  

 

About Author

About Author

Tara is a recognized industry expert with more than 20 years of experience working with: PCB engineers, designers, fabricators, sourcing organizations, and printed circuit board users. Her expertise is in flex and rigid-flex, additive technology, and quick-turn projects. She is one of the industry's top resources to get up to speed quickly on a range of subjects through her technical reference site PCBadvisor.com and contributes regularly to industry events as a speaker, writes a column in the magazine PCB007.com, and hosts Geek-a-palooza.com. Her business Omni PCB is known for its same day response and the ability to fulfill projects based on unique specifications: lead time, technology and volume.

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