Just about every place you look these days when you talk about high-speed PCB design, the signaling required for a product is, by default, differential signaling. But, differential signaling was not always at the forefront of product development. The original method of moving data was single-ended signaling. And, in some instances, it is still in use today. This article will describe the differences between single-ended vs differential transmission, which logic families have single-ended signaling and which have differential signaling, current data path needs, and what, if any, changes are looming on the horizon.
Single-ended switching specifically refers to a data path composed of a driver and a transmission line traveling over a plane or between a pair of planes and one or more inputs of loads. You decide when you have a logic state change when the rising or falling edge goes through whatever the threshold voltage is.
Lee Ritchey, founder and CEO of Speeding Edge, notes, “With single-ended signaling, if you want accurate timing, the rise time has to be very fast. The ability to precisely detect the logic state change when you go through the threshold voltage is dependent upon how fast the rise time is.”
Single-ended signaling is the least expensive method of sending logic signals as it only requires one wire and one signal pin for each data path with all of the data paths sharing the same “ground” plane.
Figure 1 depicts a single-ended data path for the BTL logic family. The BTL logic family was developed to replace ECL when CMOS became the logic family of choice. It was used to drive large data buses.
For all the aforementioned logic families, the signal is referenced at both ends, as well as at the intermediate loads, to the plane over which it travels. In most instances, the plane is logic ground, but that is not mandatory. Any noise injected into the ground path connecting the elements of the signal path erodes the logic levels that appear at the logic inputs. The common types of noise affecting ground levels are DC and AC voltage drops that occur in the ground structure because current flows through this path back to VDD. There is also the ground bounce that results when the current required to charge and discharge the logic lines as logic levels switch from 0 to 1 and passes back through the power leads of the IC. This noise on the power supply is the dominant source of EMI in most logic.
Specifically, what happens is that the current required to charge and discharge the parasitic capacitance of the transmission line and the inputs of the logic devices becomes the major source of “ripple” on Vdd, and Vdd and ground bounce. Note: Ripple is the voltage variation that appears on the Vcc or Vdd rails of power supplies. These variations can be created by the power supply itself or by varying load currents that cause the supply voltage to drop.
The foregoing current transient limits the practical width that can be used for data buses. Figure 2 illustrates the current flow that takes place in a series-terminated transmission line when the logic line switches from logic 0 to logic 1.
The current shown in Figure 2 can be calculated for any logic family. For example, if the logic family is 3.3V CMOS, the peak current is approximately 33 mA per line. If a data bus is created using this form of logic, the peak current required by the bus when all bits transition from 0 to 1 simultaneously is 33 mA times the number of bits in the bus. Table 1 shows the peak current of several logic families in amperes and at various bus widths.
These currents must be supplied by the power system. As the logic line switches from logic 0 to logic 1, this current must pass through the inductance of the leads of the IC package. When the logic lines switch from logic 1 to 0, the parasitic capacitance of the transmission line must be discharged through the inductance of the ground leads of the IC package. This is where the two types of unwanted noise, Vdd and ground bounce, and ripple, arise.
“These noise sources became so large that it was no longer possible to build packages that had inductances that were low enough and power subsystems that had enough high-quality capacitance to contain this type of noise,” Ritchey explains. “This is what led to the use of differential signaling.”
Ritchey adds, “In the final analysis, the primary advantage of single-ended switching is that it is inexpensive. The use of it has been supplanted by differential signaling. I used to try and predict when single-ended signaling would go away but it’s still found in DDR memory, so I don’t make those guesses anymore.”
Differential signaling is a broad topic and covers a number of factors. For the purposes of this discussion, the primary benefit of differential signaling is its ability to cope with substantial ground offsets between the two ends of a data path. Note: The terms differential signaling and serial signaling are used interchangeably.
Ritchey explains, “With differential signaling, you have two wires where there are equal and opposite signals on them. The data bit change takes place as the two waveforms cross. So, for a given data rate you don’t have to have near as fast an edge with differential signaling as you do with single-ended.”
Initially, the case against differential signaling was the cost. In contrast to single-ended signaling, in differential signaling, each data path requires two wires, two connector pins, two drivers, and two receivers. When data rates were relatively low and both ends of the signal path were on the same ground plane, there wasn’t a need to incur the higher cost of differential signaling. When single-ended data paths became very wide and the rising and falling edges of the signals became very fast the resulting switching noise made it difficult to meet noise targets.
Table 2 lists several types of differential signaling protocols. All of them were created to cope with the above-noted ground offsets between the two ends of the data paths.
Biphase TTL Clock Trees
Table 2. Several Differential Signaling Protocols
Ritchey notes, “Normally we convert a parallel bus into a serial bit stream. The original PCI bus configuration was 137 single-ended wires with a clock. With PCI Express I can replace that with two differential pairs, one going each way. This delivers three benefits—I don’t need the super fast rise time, I don’t have SSN on the power supply and I need far fewer wires to send the same amount of data.”
“With differential signaling, on one end you have to take the parallel data stream and turn it into a serial one (serializer). At the other end, you have to take the data stream from serial to parallel (deserializer),” Ritchey continues. “The logic required to do this used to be very expensive. As a result, we only used differential signaling when we had a severe offset problem. With today’s logic having billions of transistors, the serializers and deserializers are basically almost free and we are converting parallel buses to serial ones. With modern serial links, we embed the clock in the data so we no longer have the difficult task of matching the clock to the data. You can build systems with unbelievable bandwidth with this stuff.”
In the final analysis, differential signaling has become the silver bullet for the high-speed data paths of many of today’s electronic products, and the Internet as we know it would not exist without it. It has also become a very cost-effective approach because differential signaling does not require the very many wires associated with single-ended signaling, so the cost of the PCB is way less. Further, differential signaling will be able to handle data path needs for a long time into the future.
Would you like to find out more about how Altium can help you with your next PCB design? Still curious about single-ended vs differential transmission? Talk to an expert at Altium or read up on signal integrity tools for PCB designers in Altium Designer®.