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Confused About Differential Signaling or Clocks?

Lee Ritchey
|  Created: January 14, 2019  |  Updated: September 25, 2020

Check out this quick snippet of the Altium Podcast with guru of high speed design Lee Ritchey

The primary reason that differential signaling is dominating the digital world is that far higher data bandwidths can be achieved over a pair of wires than with parallel, single-ended signaling protocols. The Internet as we know it would not be possible without differential signaling. This information is intended to clear up any confusion about differential signaling.

Differential signaling has evolved into the primary method for connecting logic components and products together. It has replaced most of the parallel bus architectures such as PCI. The primary reason that differential signaling is dominating the digital world is that far higher data bandwidths can be achieved over a pair of wires than with parallel, single-ended signaling protocols. The Internet as we know it would not be possible without differential signaling.

Examples of differential signaling are:

  • USB
  • PCI Express
  • HDMI
  • Infiniband
  • SATA
  • Wired Ethernet
  • Hypertransport®
  • LVDS
  • ECL Long Line Drivers
  • Biphase Clocking
  • DDR Clock and Data Lines

Because differential signaling has become the protocol of choice for nearly all new designs it is important to understand how it operates and what design considerations are important and which are not. Unfortunately, there are a very large number of misconceptions about how this protocol operates and which rules in circulation are valid and which are not. Failing to understand which rules are valid may result in designs that are excessively complex or may not work properly. This chapter is intended to clear up any confusion about differential signaling.

If you want to know more about differential signaling using Altium Designer®, see how Altium Designer ensures that your differential pairs are coupled together whether you’re entering or leaving a pad or just navigating around obstacles on your board:


To make appropriate design decisions it is important to understand how differential signaling operates. Figure 4.1 is a schematic of the original differential signaling protocol. It is ECL or Emitter Coupled Logic. It is made up of two boxes or chassis, Box A and Box B. These two have their logic grounds connected with a path that has a DC offset too large for single-ended logic to properly operate. 

Figure 4.1 An ECL Differential Circuit Path

In Box A, the single-ended logic signal is converted into two signals A and A-. These are identical signals one the exact inverse of the other. What they have in common is that they are tightly timed to each other such that when a logic state change takes place the two cross in the middle, half way between a logic 1 and a logic 0. The designer’s job is to deliver these two signals to the bases of the two emitter coupled transistors in box B so they arrive at the same time. This is achieved by sending each of the signals on a parallel terminated transmission line, each usually 50 ohms and both the same electrical length. Note that there is no differential impedance involved. A good question might be how the industry came to think that differential impedance mattered. This will be answered later.

The emitter coupled pair of transistors in box B is more commonly called a current switch. Its task is to steer the current, I, up one side of the pair of the other. When the current is going up one side this represents a logic 1 and when it goes up the other side a logic 0. When the two signals, A and A-, switch logic states the voltages on the bases of the two transistors reverse and the current changes sides denoting a logic state change. So, the circuit in box B is a crossing detector. Preserving the accuracy of the crossing is the dominating problem when engineering a differential pair path. More on this later.

Signaling Protocols Tip

The reason for using differential signaling is the fact that the grounds in the two boxes are too far apart to permit reliable single-ended logic operation. Compensating for the DC offset between the two ends of the logic path is achieved by the fact that the two transistor emitters in box B are sitting on a current source, I, that allows them to move up and down as box A moves up and down. The collectors of the two transistors in box B are also current sources. Thus, the two transistors in the box B, the current switch, can move up and down with box A over a wide voltage range successfully dealing with the DC offsets and delivering a valid logic signal to box B.

With wired Ethernet, this DC offset problem is solved by using transformers at each end of the twisted pair that connects the two boxes.


Notice in Figure 4.1 that there are two independent transmission lines, one for A and one for A-. Each is parallel terminated in the impedance of that transmission line, usually 50 ohms. Neither one of these transmission lines knows the other exists and can do its job independent of what is happening on the other line. A good question is where the idea that a differential impedance was necessary or why tightly coupling these two lines to each other was important came from.

Figure 4.2 is a diagram of how the original LVDS circuit was designed. Notice that there is a Vref to which each of the parallel terminations are connected. When one side is at the logic high or 1 and the other is at a logic low or 0, the net current into or out of Vref is zero so long as the two signals cross in the middle as they were designed to do. Under these conditions the conclusion was drawn correctly that this connection was not required and was omitted in most designs resulting in two 50-ohm resistors connected in series. It seemed logical to replace these with a single 100-ohm resistor, hence the notion that a 100-ohm differential impedance was required.

This arrangement ceases to be acceptable when data rates are very high, such as 2.5 Gb/S and higher. If there is no misalignment of the two edges (skew) the circuit works fine. As soon as the two edges become misaligned in time they no longer cross in the middle and some current needs to flow into or out of Vref. If the Vref connection is missing the edges are eroded resulting in performance degradation.

Figure 4.2 The Original LVDS Circuit


From either Figure 4.1 or 4.2 it can be seen that each side of a differential pair needs to be parallel terminated in the impedance of the transmission line it terminates. In almost all cases these lines will be 50-ohms. For all but classic LVDS the terminations are located inside the IC package on the IC itself and will be two 50-ohm resistors connected to the equivalent of Vref. In the case of classical LVDS, the designer must place the terminating resistors at or after the last load. If there is no Vref termination voltage, a single 100-ohm resistor across the input to the receiver will be good enough.

Several of the protocols listed at the start of this chapter recommend an impedance other than 100-ohm differential of 50-ohm single ended transmission lines. For example, LVDS specifies 93 ohms differential or 46.5 ohms single ended. If the bulk of a design is 50 ohms, and most will be, this forces the stack up design to accommodate two different impedances, which is not desirable. By examining all these protocols, the author has determined that all of them, including DDR data and clock lines will work properly with 50-ohm lines. Therefore, it is not necessary to have two different impedances in the same stackup, thereby simplifying routing.


In some conferences it has been said that tight coupling is a good thing to do. The usual reason given is that this provides common mode noise rejection. Figure 4.3 is a diagram of a differential pair routed to the common 5-mil line, 5-mil spacing rule with a driven line next to it. These transmission lines are in a layer called offset stripline. If the reader refers to the crosstalk discussion in Chapter 2, it can be seen that the noise coupled into the near member of the pair, DIFF A, is much larger than that coupled into DIFF B, 12% vs 2%. This is not common mode rejection. For there to be common mode rejection the field strength of the inducing signal would need to be the same intersecting both members of the differential pair. This is not achievable with traces in a PCB. Designers counting on this may find they have a severe crosstalk problem.

Since common mode noise rejection cannot be achieved in a PCB, what a designer must do is assume that each member of a differential pair is a single-ended trace and make sure that there is enough space between it and any other signals that might cause a crosstalk problem.

Figure 4.3 A Differential Pair in a Stripline Layer with an Offending Signal Routed Alongside

Tight coupling a differential pair is NOT a good thing.

Even if the crosstalk from tight coupling may not be an issue, there are those who still maintain that tight coupling of a differential pair is a good thing. The author has heard this at several conferences. Figure 4.4 depicts a tightly coupled differential pair operating at 3.125 Gb/S on the left-hand side and a loosely coupled pair on the right-hand side.  Clearly, tightly coupling the pair results in a worse signal than loosely coupling them.

Why does the closely couple pair on the left in Figure 4.4 look worse than the loosely coupled pair on the right in figure 4.4?  The trace spacing on the left is 5-mil lines with 5-mil spacing. The trace width on the right above is 10-mils with a 15-mil space. In both cases, the designer set the trace width so that the differential impedance is 100-ohms or the single-ended impedance is 50-ohms.

The difference in amplitude of the two signals is the result of copper loss with the tightly spaced example. The reason that the left side trace width is 5-mils and the right side is 10-mils is that when two transmission lines are placed close to each other, each drive the impedance of the other down. To get back to 50 ohms, each trace must be made narrower driving up the copper losses.

Figure 4.4 Tightly Coupled vs. Loosely Coupled 3.125 Gb/S Differential Pair

There is a second consideration that may be more important than the loss issue. If the transmission lines in the left side example must be separated to route them through a connector pin field or the rows of vias under a BGA, they will no longer interact, and their impedance will jump up to 72 ohms. This is a catastrophic impedance change and cannot be allowed. Therefore, if the route starts tightly coupled it must remain coupled for the entire length of the route. Routing may become difficult, if not impossible, with this restriction. Experienced designers of high-speed differential pairs have learned that the better spacing rule is a “not closer than” rule. What this means is selecting a spacing that avoids this unwanted interaction. Figure 4.5 shows how the impedance of two 50-ohm transmission lines interact as the spacing is decreased between them. The example is for a stripline layer like that shown in Figure 4.3. Notice that with a 10-mils spacing the impedance change is about 0.5 ohms or 1%. Whether this amount of impedance change is acceptable depends on how much degradation can be tolerated, but in nearly all cases will be acceptable. If it is, we have our “not closer than” spacing rule. If spacings are wider, no harm is done.

Figure 4.5 Impedance vs Spacing for Off-center Stripline Transmission Lines


As noted earlier in this section, differential signaling relies on the crossing of two equal and opposite signals to detect a logic state change. Skew is a measure of how much the arrival time of the two members of the differential pair is different. If the arrival times are too far apart, or the skew is too large, the receiver will not accurately detect logic state changes and the link will fail. The purpose of length matching is to minimize the skew in a differential pair. The designer needs to make a proper tradeoff between the tightness of the length matching tolerance and how difficult it is to match the lengths. For example, the LVDS standard states that the two edges can arrive as much as 400 picoseconds apart and the protocol will not malfunction. With the velocity of signals in PCB materials that is equivalent to about 2.4 inches or 6 cm. The LVDS design guide specifies length matching must be done to 100 mils or 2.54 mm. Clearly, the author of this requirement was too conservative and made layout of these signals more difficult than it needed to be.

Table 4.1 Data Speeds and Unit Intervals

It has been demonstrated that if the length mismatch, or skew, between the two sides of a differential pair is no more than one fourth of a unit interval the link will work properly. A unit interval (UI) is the duration of a single data bit at a given data rate. Table 4.1 shows the more common data rates found in high speed protocols and their unit intervals. Also listed is the quarter UI in picoseconds along with what it is equivalent to in mils in a PCB.

What is skew?

A potential source of skew that is not obvious is that caused by the irregular nature of woven glass cloth used as reinforcement in all laminates. Figure 4.6 shows a view of commonly used glass cloth weaves know as 1080 on the left and 3313 glass cloth on the right. Each photo has a 3.5 mil wire to create a sense of scale between the glass bundles and the traces routed over them.

1080 glass weave is the most common glass style used to create 4-mil cores. Notice that the glass fibers are in tight bundles with large voids in between that are filled with resin. The dielectric constant of the glass is about 6 and the dielectric constant of the resin is below 3. This cause two things to happen as a trace runs on and off the glass bundles as shown on the left in Figure 4.6. First the impedance varies over a very wide range. This is shown in Figure 4.7 on the left. Second, the velocity changes substantially from slow on a glass bundle to fast in the resin. If the two members of a differential pair do not travel on and off the glass 1080 glass weave in exactly the same manner, they will experience different velocities that will result in skew.

The solution to this problem is to spread the glass out as is shown with 3313 in Figure 4.6

Figure 4.6 1080 and 3313 Glass Cloth with 3.5 mil Wire for Scale

Figure 4.7 Impedance vs Length for a Trace on 1080 Glass vs. 3313 Glass

The author has constructed test PCBs that have as much as 62 picoseconds of skew in a differential pair 14 inches (31 cm) long. The details on how to avoid weave-induced skew is beyond the scope of this document. It is known to cause failures at data rates of 5 Gb/S and higher.


Jitter is defined as the movement in time of the switching edges from bit to bit relative to the clock used to lock in the data at the receiver. If the jitter becomes excessive the data path will fail. Most of the protocols listed at the start of this chapter have maximum jitter specifications.

Figure 4.8 illustrates how one can calculate the amount of mismatch that can be allowed to minimize jitter resulting from the uncertainty of detecting crossings accurately from data bit to data bit. When the two signals cross in what is often called the “straight” part of the rise and fall time, the interval between the tick marks on the waveforms at the top of Figure 4.8, the bit to bit jitter (variation in relation to clock signal) is minimized. If the two waveforms are misaligned as shown in the lower waveform in Figure 4.8 a data change will still be detected, but the bit-to-bit accuracy or jitter will be worse and may result in clocking errors.

To determine how much misalignment is acceptable the calculation involves measuring the time between the tick marks in Figure 4.8, converting that to length and dividing that in half to arrive at a ± length matching tolerance.

Figure 4.8 Differential Signal Crossing and Length Matching


There are a wide variety of rules for routing differential pairs in circulation around the industry. Some of them are:

  • As tight as possible
  • As turns are required, make sure there are the same number of turns in each side of the pair
  • When layer changes are required, place “ground vias” beside each of the layer changing vias

If one reflects back to all the discussions above, the first thing that is observed is that the two members of a differential pair are actually two single-ended transmission lines that do not know that the other member exists. Therefore, all the rules listed above do not apply. Here are some conclusions one can draw from the above discussions.

  • It is not necessary to route a differential pair side by side, although it is convenient to do so just to keep track of the two.
  • It is not necessary to route them on the same layer.
  • It is not possible to route both members of a differential pair between a 1 mm pitch BGA without experiencing the problem shown in Figure 4.4.
  • If the problem in 4.4 is not an issue, there will be tolerancing problems that make satisfying insulation thickness and other requirements related to reliability and manufacturability difficult.
  • It is better to route the members of a differential pair to the “not closer than” rule.
  • Ground vias where traces change layers are not necessary.

Route each member of a differential pair as a stand-alone transmission line like all of the other single- ended transmission lines observing the length matching requirements.


AC coupling capacitors are sometimes required when the DC offsets between the two ends of a differential pair path exceeds the ability of the receivers to deal with it. In the case of PCIExpress the capacitors are required at all times, even when there is no DC offset issue. The reason is that the system uses them at turn on to detect that there is a load on the output of the switch IC.

The question often asked is where the AC coupling capacitors should be located. Some examples are:

  • Near the driver
  • Near the receiver
  • Exactly side by side
  • With the “ground” removed from under the capacitor mounting pads

Transmission lines are linear circuits so all things being equal it should not matter where they are located. As long as there are no vias used to connect them it will not matter where they are located. In other words, if the traces remain on the same layer as the component mounting pads it won’t matter where they are located.

As long as the data rates are low, below about 3 Gb/S, even with connecting vias it won’t matter where they are located. Reference 1 at the end of this chapter is a discussion of how vias used to connect to component pins and to change layers may cause serious problems at high data rates. (See reference 1.)  The design guide for PCIExpress has a section dealing with how to deal with the vias required for the connector pins.

There is a rule of thumb that states that removing the ground under the mounting pads of the AC coupling capacitors improves signal integrity. This rule is not accompanied by any proof that this is necessary or valuable. The author has constructed a test PCB with identical differential pairs using AC coupling capacitors one with the ground removed under the mounting pads and one with the ground intact. The measured data showed that there was very little difference. What difference there was showed that removing the ground caused a small amount of degradation as compared to leaving the ground intact.


One of the most difficult tasks that faced designers using wide, parallel data buses was the need to keep all data and address lines the same length as the clock signal to insure accurate clocking of the data. Almost all the differential signaling protocols are designed with the clock embedded in the data with a complex encoding scheme. This has eliminated the need to do length matching between data, address and clock.


Some might think that CMOS differential signaling is different from the ECL example used in Figure 4.1 to explain how this protocol works. Figure 4.9 is the schematic of an LVDS differential pair. As can be seen, there are two transmission lines delivering two signals to a current switch in Box B as was the case with the ECL example. The primary difference between these two circuits is the current sources used to deal with ground offsets are located in the drive end of the path for LVDS and in the receiver end for ECL. In both cases, the receiver functions as a crossing detector to detect a logic state change.

Figure 4.9 LVDS Differential Pair


When data paths are long and the data rates are high, losses along the path begin to be important sources of signal degradation. The primary sources of loss are losses in the dielectrics of the laminates and copper losses in the traces themselves. New laminates have been developed that minimize their losses. Copper losses have been minimized by making the surface of the traces very smooth. When speeds reach the point where losses are a consideration, the designer must perform simulations using accurate models of the copper, the laminate and the circuits themselves to insure the losses in the proposed design are within limits.

Progress in the design of both transmitters and receivers over the last decade has resulted in serdes (the driver/receiver pair) that can compensate for losses in the path as large as 38 db. This has allowed the industry to design PCBs that operate at 28 Gb/S and higher with relative ease.


Differential signaling has emerged as the primary method for transferring data between source and load. It has replaced nearly all parallel data transfer protocols. It is a very straight forward, easy to use technology. The rules necessary to achieve stable performance are quite simple and brief. All the protocols using differential signaling are crossing detectors. The primary mission of designers using these signaling protocols is to insure the places where the two sides of a differential pair cross are made stable and that there be large enough signals at the receivers to reliably detect logic state changes.


  1. 1. 7-TA3- Short May Not Be Better- Mike Steinberger, et al. DesignCon 2010
  2. Ritchey. Lee W, et al, 5-TP5 High Speed Signal Path Losses as Related to PCB Laminate Type and Copper Roughness, DesignCon 2013
  3. Loyer, Jeff, et al, “Fiber Weave Effect: Practical Impact Analysis and Mitigating Strategies”, DesignCon 2007
  4. DC15-8 Does Skew Really Degrade SerDes Performance- Istvan Novak, et al
  5. McMorrow, Scott et al, “Impact of PCB Laminate Weave on Electrical Performance”, DesignCon, Fall 2005.

Learn more about High Speed Design and listen to the OnTrack Podcast with Judy Warner and guest Lee Ritchey. Watch the whole episode here:


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About Author

About Author

Lee Ritchey is considered to be one of the industry’s premier authorities on high-speed PCB and system design. He is the founder and president of Speeding Edge, an engineering consulting and training company. He conducts on-site private training courses for high technology companies and also teaches courses through Speeding Edge and its partner companies. In addition, Lee provides consulting services to top manufacturers of many different types of technology products including Internet, server, video display and camera tracking/scanning products. He is currently involved in characterizing materials for ultra high speed data links used throughout the Internet.
Prior to founding Speeding Edge, Ritchey held a number of hardware engineering management positions including Program Manager for 3Com Corporation in Santa Clara and Engineering Manager for Maxtor. Previously, he was co-founder and vice president of engineering and marketing for Shared Resources, a design services company specializing in the design of high-end supercomputer, workstation and imaging products. Earlier in his career, he designed RF and microwave components for the NASA Apollo space program and other space platforms. Ritchey holds a B.S.E.E. degree from California State University, Sacramento where he graduated as outstanding senior. In 2004, Ritchey contributed a column, “PCB Perspectives” which appeared on a monthly basis in the industry-renowned trade publication, EE Times.

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