What Goes into PCIe 5.0 Layout and Routing?
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PCI-SIG has been busy pushing the limits on standardized data rates between processors and computer peripherals. While the standards group doesn’t have a direct hand in component development, the release of the PCIe 5.0 specification in 2019 and the upcoming release of the PCIe 6.0 specification in 2021 shows a clear intent to standardize peripherals for data-hungry applications. Some applications will inevitably include AI in the data center, 5G, and ultra-fast NICs.
A doubling of the data rate from PCIe 4.0 to 5.0 already makes life difficult for IC and packaging designers, but it also complicates matters on the PCB and in mating connectors. It all stems from the signalling bandwidth, which gets pushed up to higher frequencies each time there is a new PCIe generation. Here’s how PCB designers will have to cope with these bandwidth difficulties when designing PCIe devices.
Like any high speed interface, PCIe brings a particular set of challenges to layout and routing. The traces, I/Os on an IC, connectors, and even the substrate material will place limits on the bandwidth a board can accommodate while keeping losses within spec. We’ve discussed a variety of loss mechanisms throughout this blog, so I’ll briefly summarize the important loss sources in high speed channels (including PCIe lanes) here:
- Conductor losses: this includes inherent DC resistance due to the conductor cross section.
- Dielectric losses: Excitation and relaxation in the PCB substrate attenuate the electric field as it propagates through a high speed channel.
- Copper roughness losses: All etched copper on PCB laminates is rough (both electrodeposited and rolled), and copper roughness needs to be modeled correctly when performing impedance calculations.
- Resonant power loss: This fiber weave effect results from periodic loading in loose fiber weaves, resulting in power losses at particular frequencies as cavities in the substrate are excited.
Note that radiation losses would also be considered in microstrips when the substrate thickness is rather large (e.g., 30 mils in this technical article from John Coonrod), but these losses can be ignored in closed waveguides or in stripline routing. These losses can also be ignored in higher layer count boards or for microstrips on very thin laminates. At the 32 Gbps data rates in PCIe 5.0, FR4 is no longer a viable option and a low-loss laminate needs to be used.
In PCIe 5.0 channels, dielectric and roughness losses can be addressed at the PCB substrate level by selecting the appropriate low-loss laminates. Mating connectors and vias will contribute their own losses, normally through reflection due to impedance mismatch within the signal bandwidth. Losses are limited in the PCIe 5.0 spec and are limited to -37 dB at a lane’s Nyquist frequency (16 GHz for 32 Gbps bitrate). How you arrange your components on a board, or on multiple boards, will determine the number of via, connectors, and maximum interconnect length you can use in PCIe 5.0 layout and routing.
Once you’ve settled on a PCB substrate material and you’ve designed traces to have sufficiently low losses, you can proceed with routing and layout for PCIe devices. PCIe devices, daughterboards, and host processors are laid out in point-to-point topology. PCIe PHY modules, devices, and processors may be placed on the same board or separated on different boards with a connector (orthogonal, edge, or mezzanine).
One important point in routing PCIe links is to place an AC coupling capacitor. If you’ve never worked with PCIe, this is one of those points that might get buried in a datasheet. Different IC vendors will recommend different AC coupling capacitor values for their products (e.g., Xilinx FPGAs recommend 100 nF). Like any other coupling capacitor, the purpose is to remove DC offset along each end of the link while still allowing data pulses to propagate between components.
Routing in PCIe lanes should follow best-practices for differential signals (85 Ohms differential impedance with length matching across a Diff Pair Net Class and proper spacing). Note that, for connectors placed between long sections of traces, it’s common to see large impedance deviations (up to 15 Ohms) on PCIe-compliant connectors. What’s more important is how this mismatch affects the S-parameters (specifically, return loss), which needs to be determined from testing to check whether a connector, layer transition, or overall routing style is acceptable.
Finishing Up and Testing
When it comes time to test a prototype or test coupon, the PCIe 5.0 spec allows a differential breakout channel to be routed from a DUT to a test fixture. To evaluate loss in your PCIe channel, place an identical breakout channel on the board and use this to de-embed the S-parameters for the channel. You can then determine whether channels will meet the PCIe 5.0 specs and if any other design changes are needed.
Until more PCIe 5.0-compatible devices hit the market, it doesn’t hurt to design to these specs regardless. Intel’s PCIe 5.0/DDR5 compatible Sapphire Rapids CPUs will be available in 2021, and AMD will soon follow with competitive products in 2022. Thankfully, the PCIe 5.0 specs are electrically backward-compatible with earlier PCIe generations. It likely won’t be much longer after that, and we’ll be talking about PCIe 6.0.
When you’re ready to start designing a PCIe 5.0 layout and route signals around your board, you need the high-speed design tools in Altium Designer®. You’ll have the tools you need to route high speed boards for any application and prepare them for full-scale manufacturing. When you need to collaborate with others on your design team, you can share and track revisions through the Altium 365® platform, allowing designers to work from home and reach unprecedented levels of efficiency.
We have only scratched the surface of what is possible to do with Altium Designer on Altium 365. You can check the product page for a more in-depth feature description or one of the On-Demand Webinars.