PCB Design For Test—Test Structures And Types Of Tests, Part 1

November 4, 2019 Kella Knack

PCB Design For Test. Test Structures And Types Of Tests, Part 1

An important part of any high-speed design is making sure it can be tested successfully during manufacture and operation. Since these tests are performed significantly downstream from the PCB design process, they are not often properly and thoroughly accounted for as part of this process. This article will address two important aspects of the design for test process: creating test structures (aka test point connections) within the board, and describing the tests themselves and how the test points are connected to the various devices used for testing.

Part 1 of this article will describe the test structures necessary for accessing the various test equipment while Part 2 will address how the test structures are attached to the equipment so that the outcome of the connectivity tests can be confirmed.

The PCB Testing Process

The goal of the PCB test process is two-fold: To confirm that the PCB operates as specified and that all of the PCBs within a given lot satisfy this requirement.

In order to determine the “state-of-the-state” of today’s PCB test process, it’s useful to address the history of testing. Traditional bare board PCB testing involved net list testing of the PCB to a CAD generated net list in order to insure there were no opens or shorts. Following this, it was necessary to ensure that the quality of outer layer plating was such that it would successfully tolerate the assembly process. This was usually done by taking one PCB from a lot, referred to as a solder sample, and performing solder tests on it. In addition, the PCB fabricator might have sawn a piece from one of the PCBs and then performed a micro-section test on it to ensure that the copper plating of the holes was properly done. If all the foregoing tests were positive, the entire lot of PCBs was released for use.

As the speeds of logic circuits have increased, there are several additional factors that need to be addressed including:

  • Ensuring that the impedance of the signal traces are within tolerance.
  • Ensuring that the interplane capacitance of each power subsystem is adequate.
  • Ensuring that all of the dielectrics have the correct dielectric constant so that propagation velocities are as specified.
  • Ensuring that all of the PCB layers are in the correct order. (In today’s manufacturing environment it is possible to have just one PCB out of a batch that will have the layers in the wrong order).

There are three places in the manufacturing process where testing is performed:

  • Bare board test.
  • Assembled board test.
  • Repair center test.

Determining Which Test Structures Are Required

The most obvious test structure for a high-performance PCB is an impedance test trace. This trace must be added for each signal layer that has an impedance specification associated with it. In addition, there needs to be a way to measure the plane capacitance of each supply voltage. There also needs to be a way to ensure that all of the layers are in their proper place within the PCB stackup; that they are of the correct thickness and that the dielectrics separating them are of the correct thickness and glass style. Taking all of these  elements into account necessitates the creation of the following test structures:

  • Impedance test traces.
  • Access points to power and ground plane pairs.
  • A method for ensuring that the layers are correctly stacked.

Where Should Test Structures Be Located?

In addition to creating the right test structures, there is the need to ensure their proper placement. Traditionally, these structures were placed on a special test coupon. This coupon was not part of the PCB itself but instead was built into the material surrounding the board fabrication panel. The advantage of this process was that the coupon could be taken to the laboratory and analyzed without the need to cut samples from any of the PCBs within a lot. These coupons could be standardized to speed up the testing process which was good for the PCB fabricators. Figure 1 is a typical test coupon that contains only impedance test traces.

A Typical Test Coupon

Figure 1. A Typical Test Coupon

The problem with a test coupon is that there is no way to guarantee that the trace widths within that coupon are the same as those in each layer of the PCB it is intended to represent. We have seen instances where the test coupon measured one set of impedances while the impedances on the PCB were entirely different. This was due to a CAD error on the part of the fabricator when the coupon artwork was created. Another problem is that test coupon can be separated from the PCB at final fabrication and it is often not available when it is needed. We have been called in to troubleshoot PCBs after they have been assembled and the coupon has been stored somewhere else during the assembly process. This results in not having the traceability necessary to troubleshoot design problems.

Test Structure Examples

The foregoing disadvantages of dedicated test coupons far outweigh their advantages. Therefore, we have found the best approach is to include the test structures within the body of the PCB itself. The obvious advantages to this methodology are:

  • The test structures are always with the PCB they are intended to represent.
  • The features in the test structures are created by the PCB designer rather than the PCB fabricator.

Impedance Test Structures. Figure 2 shows one way to design impedance test traces. This diagram shows both a single-ended impedance test structure and a differential test structure. If a PCB has eight signal layers on which impedance is being controlled, the structure can be expanded to provide a test structure for each layer.

Sample Impedance Test Traces

Figure 2. Sample Impedance Test Traces

The spacing and size of the vias at the ends of the test traces are important. In order to permit the use of standard impedance test probes, the distance between the via at the end of the trace and its designated ground via needs to be 100 mils (2.54 mm). The diameter of the drilled hole needs to be 30 mils (.762 mm) to allow the probes to fit properly.

In Figure 2, the traces are three inches long (7.62 cm) and straight and there is access to the vias at both ends. 

(They need only be 1” long (2.54 cm) to get an accurate impedance measurement.) If there is not enough room on a signal layer for the test trace to be straight it is fine if it is bent. Also, while it is not necessary to have access vias at both ends of the test trace it is handy to have them.

The photos in Figure 3 show two ways to implement PCB test traces. The example on the left hand side of the figure has a ground via for each test trace. The example on the right has a single ground via in the center with four test traces sharing it. Both are acceptable ways to implement impedance test traces. It is important to maintain the 100-mil hole spacing and 30-mil drill diameter in order to facilitate testing. Also, each test trace is labeled in the silkscreen with its layer number. This is an important factor when it comes time to do the actual testing.

Methods for Implementing Impedance Test Traces

Figure 3. Methods for Implementing Impedance Test Traces

As an aside: To address the question: “To What Plane Should the ‘Ground’ Via For a Test Trace Be Connected?” We can refer again to Figure 3. On the right side of the figure there are four test trace vias surrounding one “ground” via. Here, the frequently asked question becomes: “Does the TDR (Time Domain Reflectometer) ground need to connect to the plane just under trace being tested in order to obtain an accurate impedance reading”?

To address this we have built test structures into all of the PCBs that have been used to check out the various rules of thumb addressed in both volumes of our book. In each instance, there has been a test structure similar to the one shown in Figure 3 but the test trace was attached to the middle via and each of the four surrounding vias connected to a different plane in the PCB. When the TDR is attached to any of the four “ground” vias, the impedance measured is the same. This is because all of the planes have been “shorted” together at the frequencies involved in the measurement by the interplane capacitance or by the ground vias of the components.

Impedance Test Structures for Power Planes and Bypass Capacitors. Figure 4 illustrates how to design access points that are used to measure the impedance of the power planes and the bypass capacitors. 

Test Structure for Measuring Power Planes with Capacitors Connected

Figure 4. Test Structure for Measuring Power Planes with Capacitors Connected

This important test verifies that the decoupling capacitor population is correct for each power supply voltage. Two of these test access points are required for each power supply voltage on a PCB. The two structures should be placed at least one inch apart and labeled with the voltage to which they connect. One point allows a signal to be injected into the plane capacitor and the second allows measurement of the resulting voltage

Stacking Stripes 

The stacking stripes test structures shown in Figure 5 are used to check several things about the way in which a PCB is built. 

Stacking Stripes

Figure 5. Stacking Stripes

Strips of copper are plotted along one edge of a PCB so that when the PCB is cut from the panel the strips are visible to the naked eye. Notice that the strip in each layer gets longer than the one above. This stair step construction makes it possible to determine that all the layers are in the correct order. It can be readily observed that the stair steps get longer with each layer the further down you go into the PCB. A reasonable question to ask is how they could ever be out of order. In reality, there are many places in the design and fabrication process where the order of the layers can be mixed up. One is in the preparation of the photo-tools used to etch the PCB layers while the other occurs during the actual laying up of the individual layers during the lamination process. Figure 6 is a photograph of the stacking stripes in a 24-layer PCB showing just such a mix up. Layer 22 is where layer 11 should be and layer 11 is where layer 22 should be. This happened because the CAD operator mislabeled the CAD files when the Gerber data was being prepared. The fabricator just followed that wrong order. If this PCB had been assembled, it would not have functioned properly. Without the stacking stripes, there would have been no way to determine what was wrong.

A PCB With The Layers Stacked Incorrectly

Figure 6. A PCB With The Layers Stacked Incorrectly

A second feature in the stacking stripe set is a small section of trace plotted such that when the PCB is cut from the panel it is visible end on. This trace is plotted 5-mils wide (127 microns). By measuring the actual etched width it is possible to determine if the signal layer is properly etched and not over or under etched. Using this and the stackup dimensions, it is possible to troubleshoot what is amiss when the impedance is not within specification and determine what corrective action needs to be taken.

An Enlarged View of Stacking Stripes

Figure 7. An Enlarged View of Stacking Stripes

Last, stacking stripes allow you to examine the overall   of the PCB by measuring the thickness of the dielectric layers and the copper layers. Figure 7 is an enlarged view of an actual set of stacking stripes showing the glass fibers in each dielectric layer, the copper thickness and the 5-mil traces protruding from the PCB. This provides a complete audit of the stackup without the need for destructive testing. Best of all, these features are a part of every PCB, so it is easy to check the cross-section and impedance long after the PCB has been assembled, should this be necessary.

One objection that is raised when stacking stripes are proposed comes from the old standard that “no exposed copper be allowed at the edges of a PCB.” The way that standard actually reads is that no copper attached to any circuit inside the PCB is allowed to be exposed at the edge of a PCB. This requirement is easily met by making sure these copper strips are isolated from all of the circuits inside the PCB itself. Adding the test structures described above adds little or no cost to the finished PCB. The only real cost is the time the PCB designer must invest to add these features to each new PCB file. In our experience, CAD departments are slow to get the first structures designed, but once they get some experience, this task adds very little to design time.

The Cost of Not Having Test Structures

From all of the discussions so far, the cost of not having test structures should be clear. However, in many cases the cost is not obvious. Without test structures there is no way to isolate a PCB failure such as an incorrect impedance, a wrong stackup, the wrong glass fiber or the wrong copper thickness. These undetected mistakes are grouped under that broad, frustrating group of “flaky” PCBs. As a result, there is no mechanism for taking corrective actions.

If no stacking stripes were used on the PCB in Figure 6, manufacturing would have assembled about $5,000 worth of parts on the PCB. It would never have worked properly. In addition, those people responsible for debug would have invested countless hours with no positive results. What is that worth? Perhaps the whole program would be put at risk but adding some “no-cost” stacking stripes will prevent this from occurring.

Examples of Failures Caught By Test Structures

The PCB in Figure 6 is one of the best examples of failures caught by using test structures. (In this case, all of the impedances were correct because the layers that were swapped were power and ground planes). A not so obvious failure that was caught through test structures was an assembly with the wrong type of bypass capacitors called out on the bill of material. And, as noted above, incorrect impedance values are the remaining things test structures catch.

Are There Any Disadvantages to Using Test Structures?

Other than the surprise exhibited by fabricators and others who are not accustomed to seeing these test structures, there are no disadvantages to building them into a PCB design. Sometimes it is claimed that there is no room for them on a crowded PCB. In our experience, there has always been room. It might require that the designer use a little imagination, but there is always room. Figure 8 is a picture of a PCMCIA card with stacking stripes along the top edge.

A PCMCIA PCB With Stacking Stripes

Figure 8. A PCMCIA PCB With Stacking Stripes

Summary

For engineers to design test structures into PCBs and fabricators to build them requires only a very minimal amount of time and cost. However, the long term savings can be significant and can mean the difference between overall product success and failure. Part 2 of this article will describe how testing connectivity is done during various stages of the entire board process—bare board test, assembled board test and repair center test.

To create the best layer stackup in PCB design you need the best layer stack manager tools that are found in Altium Designer®. Would you like to find out more about how Altium can help you with your next PCB design? Talk to an expert at Altium.

References:

  1. Ritchey, Lee W. and Zasio, John J., “Right The First Time, A Practical Handbook on High-Speed PCB and System Design, Volume 2.”

  2. Ritchey, Lee W., “Test Structures Needed for Multilayer PCBs” Current Source Newsletter, Fall 2004.

About the Author

Kella Knack

Kella Knack is Vice President of Marketing for Speeding Edge, a company engaged in training, consulting and publishing on high speed design topics such as signal integrity analysis, PCB Design ad EMI control. Previously, she served as a marketing consultant for a broad spectrum of high-tech companies ranging from start-ups to multibillion dollar corporations. She also served as editor for various electronic trade publications covering the PCB, networking and EDA market sectors.

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