Bandwidth Requirements For Differential Signals

Kella Knack
|  October 16, 2020
Bandwidth Requirements For Differential Signals

As noted in an earlier article, along with series-terminated transmission lines, differential signals serve as the links for most CMOS devices. One of the key differences between single-ended signals and differential signals is that the bandwidth requirements of a differential signaling path are much less demanding than those required for a single-ended signaling path operating at the same frequency. This article provides an overview of the benefits of differential signaling and how it operates in a working electronic product.

A Quick Overview of the Benefits of Differential Signaling

The first data point about differential signals is that they usually have a much smaller signal swing then single-ended signals and are almost always parallel terminated. This results in the total current drive being almost constant as it switches directions on the signal wires. The specific advantages of differential signals include:

  • The power load is current and constant.
  • Both the signal current and the return current for the two wires are equal and in opposite directions.
    • This yields a constant total current on package interfaces.
  • Since both lines in differential signaling are traveling in parallel, they tend to have the same amount of injected noise from coupling to the plane over which they travel.
    • Differential signals do not receive the same amount of noise coupling from adjacent traces.
  • The differential receiver eliminates the problems resulting from ground drops or power supply shifts between components.
  • Differential signals can operate at much higher speeds than single-ended signals.

Given the previous, it would seem that using differential signals is a “no brainer.” But, there is one drawback—they require serializing the data at one end and deserializing the data at the other end.

There is also a misconception that is commonly applied to differential signaling: The characteristic ascribed to differential signaling is that side-by-side routing of the pairs in a PCB provides common-mode noise rejection. As discussed in previous articles, this is not the case.

How The Different Types of Logic Operate

Real Logic

Before delving into how single-ended logic operates vs. how differential logic operates, it’s useful to review how real logic operates. This is addressed in the following points.

  • Real logic signals are not perfect square waves.
  • Real drivers have a limited ability to generate higher harmonics of the clock frequency resulting in rounded edges, as shown in the graphic on the left-hand side of Figure 1.
Typical Single-Ended Logic Signals
Figure 1. Typical Single-Ended Logic Signals.
  • Slower drivers produce slower edges as seen on the right-hand side of the graphic in Figure 1.

Single-ended Logic

The key operational characteristics of single-ended logic include:

  • Single-ended logic paths have inputs that respond to the rising and falling edges of the logic signals.
    • When a rising or falling edge passes through a threshold voltage (usually midway between a logic 1 level and a logic 0 level), a logic change is detected.
  • How precisely the timing of the logic changes depends on how fast or sharp that edge is.
    • Slower edges result in the less precise detection of when a logic state changes.
  • To preserve logic precision, the signal path must pass several higher harmonics of the clock frequency.
  • Harmonics is the term that is used to describe the distortion of a sine wave by other waveforms that are of different frequencies.

Important Details Regarding Signal Harmonics vs. Rise Time and Their Impact on Single-Ended Data Paths

To understand how single-ended signals operate, it’s helpful to take into account the role of signal harmonics vs. rise time. These data points include:

  • The Fourier transformation of a waveform produces the harmonics present in the waveform as well as their amplitudes.
    • Fourier analysis is a mathematical operation on a voltage waveform that converts it from the time domain to the frequency domain or the reverse.
  • The diagram on the left-hand side of Figure 2 shows the frequency content of a logic path whose clock frequency is 100 MHz with a slow rise time. The main components are the odd harmonics of this frequency.
Harmonics in Slow Rise Time Logic Signal vs. Fast Rise Time Logic Signals
Figure 2. Harmonics in Slow Rise Time Logic Signal vs. Fast Rise Time Logic Signals.
  • The diagram on the right-hand side of Figure 2 is the same waveform like the one on the left but with faster rise and fall times. It can be seen that the higher frequency harmonics are much larger on the right side than the left.
    • A signal path with low bandwidth would cause this slowing down of the edges as shown on the left-hand side of Figure 2. This results in less reliable operation of the single-ended data path.

How A Differential Signal Operates

Figure 3 depicts a differential data path.

A Differential Data Path
Figure 3. A differential data path.

In contrast to how a single-ended data path operates, the key operating aspects of a differential signal include:

  • Differential data paths decide when a logic state change takes place by detecting when the two equal and opposite signals cross as shown in Figure 4.
Differential Pair Waveforms
Figure 4. Differential Pair Waveforms.
  • In contrast to a single-ended data path, the differential data path has a different requirement in terms of how it operates. With differential signaling, the focus is on the precision of the crossing. It does not depend on rise time of the signal. 

The salient points regarding the differential signal shown in Figure 4 are as follows:

  • As can be seen, the differential signal in Figure 4 has the appearance of an “eye”.
    • This is why this graphic is referred to as an “eye diagram” in the SI industry.
  • Two conditions are necessary for a differential signal path to operate properly. They include:
    • The “eye” must be sufficiently open to allow the receiver to detect the logic state accurately. (Some receivers need only four or five millivolts to do this.)
    • A logic state change is detected where the signals cross. The movement associated with this change must not move back and forth too much. If it occurs too often, the result will be jitter, and the signal will degrade.
    • The previous conditions are met when the signal is little more than a sine wave or the first harmonic of the clock frequency.

Based on the foregoing, the following determinations can be made regarding the bandwidth requirements of differential signals. These determinations include:

  • Based on the previous discussion regarding Figure 4, it can be determined that the bandwidth requirements of a differential signaling path are much less demanding than for a single-ended data path with a similar frequency.
  • Successful signaling with a differential data path requires a path bandwidth that is just a bit more than the clock frequency.
    • As an example, a 6.125 Gb/S data path has a clock frequency of 3.0625 GHz. A data path with a bandwidth that is little more than 3 GHz will perform properly at this data rate.
  • A single-ended data path of the same data rate would require a bandwidth of about 40 GHz to operate properly.

Summary

In contrast to single-ended signaling, the bandwidth requirements for a differential signaling path are much less demanding than those required for a single-ended signaling path operating at the same frequency. Differential signaling provides a significant number of benefits in terms of a load path that is constant and current; signal and currents that are equal and in opposite directions; signals that don’t receive the same amount of injected noise as single-ended signals; a receiver that eliminates the problems arising from ground drops or power supply shifts between components and signals that operate at much higher speeds than single-ended signals.

Have more questions? Call an expert at Altium.

References:

  1. Ritchey, Lee W., and Zasio, John J., Right the First Time, A Practical Handbook on High Speed PCB and System Design, Volumes 1 and 2.
  2. Speeding Edge 3-day Course, “Signal Integrity and System Design and Getting to 32 Gb/S, How to Design Very High-Speed Differential Pairs.”
  3. Speeding Edge 1-day Course, “Getting to 32Gb/S How to Design Very High-Speed Differential Pairs.”
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About Author

About Author

Kella Knack is Vice President of Marketing for Speeding Edge, a company engaged in training, consulting and publishing on high speed design topics such as signal integrity analysis, PCB Design ad EMI control. Previously, she served as a marketing consultant for a broad spectrum of high-tech companies ranging from start-ups to multibillion dollar corporations. She also served as editor for various electronic trade publications covering the PCB, networking and EDA market sectors.

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