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    Crystal Oscillators in Your PCB Layout Keep Frequencies Steady

    Altium Designer
    |  March 20, 2018

    Waveforms on fractal background

    For most of human history, we relied on astronomical timekeeping to plan our lives. Now we have sophisticated clocks that help us manage daily life. As modern life becomes ever more frantic, we need to keep track of fractions of a second. Electronic crystal oscillator pcb layout guidelines are the secret sauce that makes this possible.

    The output clock signal from a Schmitt-trigger oscillator or a 555 timer is controlled using an RC time constant. The problem with using these circuits is that the resistor and capacitor values do not stay constant over time. Both resistance and capacitance can change with the temperature of the circuit board. Components can also degrade as they age. These factors cause the clock’s frequency to drift over time.

    If frequency stability and accuracy are critical, a crystal oscillator is a better choice. A quartz crystal cut to a specific shape can vibrate at a specific resonant frequency, and this frequency is highly stable against temperature changes. Crystal oscillators can output stable frequencies ranging from kHz to MHz if properly placed and connected in your PCB.

    Any digital system that uses a clock present design challenges. This is especially true in PCBs, where issues like parasitic capacitance and signal reflection can degrade signal integrity. Some of these design issues become more pressing at high-frequencies. Fortunately, there are some design strategies that will help maintain signal integrity in your designs.

    Minimizing Propagation Delay and Clock Skew

    Switching in logic circuits, particularly in TTL and CMOS logic devices, causes propagation delays to accumulate downstream from the clock output. While this tends to be on the order of nanoseconds, it becomes comparable to the width of the clock pulses in high-frequency circuits.

    Clock skew can occur regardless of the clock that is used in the device. Variations in trace lengths cause time delays to accumulate as clock signals are routed to various electrical components. When clock skew is combined with propagation delay, the mismatch between clock pulses in parallel traces can be significant.

    Clock skew and propagation delay can be compensated by adjusting the length of signal traces. Differential trace lengths between successive components should be made equal to minimize clock skew. Certain parallel traces may contain different numbers of components, and the propagation delay of each component should be considered when placing traces on your Printed Circuit Board.

    Avoid clock skew by matching parallel traces
    Avoid clock skew by matching parallel traces

    Ground Plane Placement

    Some PCB designers may have a tendency to run their power and signal traces directly over their ground plane. This is not recommended as incorrect ground plane placement can cause your clock circuit to function as an antenna. Not only will the circuit be susceptible to external EMI, but the circuit will also produce RF radiation that can cause EMI in other nearby circuits.

    For a particular clock frequency, the thickness of the ground plane is only 1/2 wavelength across. Since the crystal oscillator is a really a broadband current source, the clock signal and its return currents both contain a band of high-frequency components. If these currents are allowed to flow across the ground plane, you have just created a center-fed patch antenna.

    If the clock signal band overlaps with one of the ground plane resonant frequencies, a strong current can be generated in the ground plane. But if you separate the power and ground planes, radiation due to high-frequency current loops will be reduced. This will also reduce susceptibility to external EMI.

    Separate your ground and power planes to reduce EMI
    Separate your ground and power planes to reduce EMI

    Use the Right Capacitors

    Signal integrity from your crystal oscillator can be maintained by using two capacitors. One should be connected between the high voltage pin and the ground plane, and another between the ground pin and the ground plane. You will need to match the capacitors to the specific crystal you chose. The required capacitance varies for different oscillator models, even within the same manufacturer.

    Your crystal oscillator will include a load capacitance specification (usually 20 to 50 pF) that you can use to determine which capacitors to use with your crystal. Each capacitor should be double the load capacitance value, minus any stray capacitance. Stray capacitance values tend to be several pF. Don’t forget to include bypass capacitors when you make connections between your clock signal traces and other ICs on the board.

    Avoid Vias on Clock Signal Lines

    Vias can act as capacitive or inductive discontinuities in trace lines. This means that traces carrying clock signals may reflect off of vias and cause signal integrity problems. It is recommended that higher frequency signals produced by crystal oscillators not be routed through vias if possible. If vias must be used in order to maintain form factor, the traces and vias must be impedance matched to prevent reflection.

    Impedance matching between vias and traces can be done by minimizing or eliminating stubs in vias. The unused stub acts like an unterminated transmission line with significant signal degradation around its resonant frequency. Stubs generally do not serve any useful purpose and can be removed by back drilling. However, back drilling requires an extra fabrication step and can increase manufacturing costs.

    Altium Designer® has advanced functionality to route and analyze signal paths in your PCB design. The PDN Analyzer™ tool allows you to analyze signal paths in your design and diagnose problems early. To find out more about how Altium can help you design your next high-speed device, talk to an Altium expert today.

    About Author

    About Author

    PCB Design Tools for Electronics Design and DFM. Information for EDA Leaders.

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