This is the DRC You Need to Add
I was impressed that, right out of the box, the stock Design Rule Checks (DRCs) in my copy of Altium 20 pretty much covered all the bases on how to make a “standard” Printed Circuit Board (PCB).
Altium defaults to “10 mil” rules, which means that the standard spacing and widths of copper tracks is 10 mils. What's more, most of the other spacings also default to 10 mils; pads to tracks, through-holes to other pads or vias. The exceptions being the size of the sliver of silkscreen left between pads and the solder mask expansion around pads, both of which default to 4 mils.
Starting a PCB means selecting the “design rules”, a set of rules that is both supported by the PCB fabrication companies and which also helps the engineer accomplish the job. The combination of trace width and clearance, usually similar if not equal, defines the metric; i.e., 10 mil spacing is referred to as “10 mil rules”.
Exceptions exist, especially as density and complexity increase. For example, entirely different sets of design rules may exist in regions such as the area under an Integrated Circuit (IC) with a Ball Grid Array (BGA) footprint. As density increases, it is not uncommon for these rules to be listed in other units and complexity.
Designing for the Capabilities
I tend to design for “6 mil rules”, as I turn quick little designs through PCB fabricators using online ordering procedures. When setting up for a new PCB, I will decide on the range of PCB fabs I want to use, as well as an estimation of PCB fabrication budget.
Once the ruleset and type of fab house is decided, the fabrication capabilities need to be examined and translated to rules or policies which the Altium software can understand. Often I will create vendor-specific rulesets in addition to generic “x mil rule” rulesets that represent the capabilities of that vendore pretty much line by line, stat for stat.
Again as things get complicated, we respond by adapting the rulesets and the compromises in fabrication that they represent. Understanding the fabrication process comes in handy in these instances. For example, the center of the board may have the best drill-to-copper registration where rules can be bent more. To think of it another way, in cases where rules need to be bent and fabrication capabilities pushed, it is best to statistically increase the chances of success wherever possible.
Another example of bending the rules is decreasing the solder mask expansion around high density pins and pads so that there is enough solder mask left between pins/pads to act as a solder dam and prevent solder bridges, or reduce them statistically. This is clearly a tradeoff, as now there is less room for misregistration of the solder mask, which can affect solderability, or the likeliness of a solder bridge.
Some things we don’t have to worry about, sort of. If text characters (often referred to as silk screen or overlay) coincide with bare copper, the overlap will not be printed—or not usually I should say as it depends on the fab house—but my houses tend to make bare copper bare. The result doesn’t usually harm the electrical function of the board, but the “silkscreened” text may be hard or impossible to read.
Silk to Solder Mask Clearance
Herein lies the issue and why I needed one additional DRC rule; I created a Silk To Solder Mask Clearance rule as shown below taking care to check the radio button marked “Check Clearance To Exposed Copper”.
The net result is that Altium generates a list of every instance in which the text overlaps the bare copper of component pads.
Now if only someone would invent an automated function to move silk screened text off of exposed pads and vias across the board. >:/