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Microstrip Ground Plane Clearance: How Close is Too Close?

Zachariah Peterson
|  Created: May 28, 2021  |  Updated: August 24, 2023
Microstrip ground Plane clearance

If you take a look at any guidelines on sizing and calculating the width for controlled impedance traces, you’ll clearly see that the trace width is calculated without any ground to pour near the trace. However, most designers (and basic PCB layout guidelines) will state that unused areas on each PCB layer should be filled in with grounded copper pour.

There is an obvious contradiction here that is not so well discussed in the PCB design community. If you bring some ground pour near a microstrip trace, you’ve now formed a coplanar waveguide arrangement, and now the impedance of the interconnect will depend on the spacing between the edge of the trace and the copper pour. So now the question becomes, how much microstrip trace to ground plane clearance do you need to ensure you’ve hit your impedance goals?

In this article, I want to look more closely at this question. Prior explanations focus on a range of possible impedances that ignore practical design requirements in modern components. If you want to know the minimum microstrip trace to ground clearance you need to ensure controlled impedance, keep reading and you’ll find a good answer for a range of possible trace widths. The design exploration results I’ll show reveal that the same explanation also applies to strip lines on an inner layer.

The Controlled Impedance Design Process

In boards that require controlled impedance routing, there is a particular design process you’ll generally see for a specific net/group of nets when starting the design:

  • Determine the impedance target for the specific nets being considered
  • Determine the stack-up you’ll be using and where you’ll be routing
  • Choose a routing style (microstrip, stripline, coplanar waveguide, single-ended vs differential)
  • Calculate the trace width needed to give the required impedance

After everything is routed, it’s now a question of whether it’s appropriate to fill in the unused regions of the surface and internal layers with the grounded copper pour. However, this is now a question of whether the ground pour is too close to the trace. The image below shows an example of an RF trace operating at high frequency (5.8 GHz), which will then function as a feedline to an antenna.

RF microstrip ground clearance
Example of RF microstrip routing and spacing between copper pour on the surface layer.

The example above is quite important as many application notes for components with RF outputs will recommend exactly this type of routing, possibly with a via fence along the trace. The intent here is to isolate the RF trace from EMI that may come from other portions of the layout, or from some external source. However, these same application notes will generally give an overly conservative guideline on the spacing between the RF trace and the nearby GND copper pour. So just how close to the ground can you place your controlled impedance trace?

Is it a Microstrip Transmission Line or a Coplanar Waveguide?

For the moment, I want to focus on single-ended microstrips because they are conceptually easy, but everything I’m about to write applies equally to strip lines. The same ideas also apply to differential pair routing.

If the surface layer ground pours in the above image are too close to the trace, then we have a coplanar waveguide, not a microstrip. Theoretically, when the surface layer ground pours an infinite distance from the trace, then we are back to a microstrip. If you bring the ground plane clearance too close to the trace, you will alter the impedance of the microstrip due to the parasitic capacitance between the edge of the trace and the ground pour. This is why single-ended microstrip transmission line ground and single-ended coplanar waveguides don’t always have the same trace width; the coplanar waveguide generally requires a smaller width to have the same impedance as a microstrip on the same stack-up.

Microstrip ground clearance
Parasitic capacitance between the microstrip and the nearby GND pour increases the total capacitance of this transmission line.

From the above, we can see why coplanar waveguide traces may need to be smaller than a microstrip on the same layer and stack up. The parasitic capacitance increases the total per-unit-length capacitance of the trace, so L needs to be increased to compensate, thus bringing the impedance back to 50 Ohms. In the next section, I’ll use this idea to test when the ground pour is too close clearance to the trace by looking at the impedance deviation from a 50 Ohm target as a function of ground clearance.

Testing the “3W” Rule

There is actually a rule of thumb here. This is the “3W” rule, which states the spacing between the trace and the nearby ground pour should be at least 3x the trace width. As we’ll see momentarily, this guideline is overly conservative and does not account for multiple factors. In reality, the minimum required spacing will depend on:

  • The routing style (microstrip vs. stripline)
  • Whether single-ended or differential pair routing is used
  • The dielectric constant of the substrate
  • The distance between the trace and its ground plane on the next layer

Since we’re looking at a situation where you need to determine the trace width required for controlled impedance, I’m going to test the 3W rule by comparing the trace width required to produce a 50 Ohm impedance microstrip with a coplanar waveguide of the same impedance. I’ll do this for various layer thicknesses so we can see how the method for determining the intrinsic parameters of strip transmission lines affect the required ground plane clearance. Here, the goal is to determine the minimum spacing needed to produce a coplanar waveguide with the same impedance and trace width as a microstrip.


I first generated a set of curves showing the microstrip width, stripline width, and coplanar widths (interior and surface layers) required to produce 50 Ohm impedance on a 370HR Isola laminate (Dk ~ 4.1, ~0.02 loss tangent @ 1 GHz). These calculations were performed in Polar. The image below shows these results and allows trace widths for each type of trace to be compared for a specific trace-to-ground pour spacing of 5 mils.

Microstrip ground clearance
The trace width curves in this graph all correspond to 50-ohm transmission lines for all four routing styles on the same substrate. The coplanar waveguide (CPW) arrangements have 5 mil clearance to the ground plane clearance.

From here, we can see that there are specific stack-ups where a CPW and a microstrip/stripline will have 50 Ohm impedance and the same trace width, even though the ground clearance is quite close clearance to the trace in the CPW.

The next graph investigates this further. It shows the minimum trace-to-ground spacing required to produce a 50 Ohm impedance microstrip and a 50 Ohm coplanar waveguide with the same trace width. Results are also shown for a stripline and a coplanar waveguide on an internal layer.

Microstrip ground clearance comparison
Minimum trace-to-ground spacing in a coplanar waveguide (CPW) that will produce the same impedance in a microstrip/stripline for a given trace width.

The interpretation of the above graph is very simple: this shows the minimum trace-to-ground spacing in a CPW required to produce the same impedance in a microstrip/stripline when they both have the same trace width. From here, we can finally generate our test of the 3W rule. Simply divide the y-axis data by the x-axis data to produce the following graph:

Microstrip ground clearance comparison
Calculated clearance-to-width ratio for a 370HR laminate. Note that other dielectrics will have different dielectric constants, so different curves would be generated.

It’s quite clear that the 3W rule is overly conservative, except in cases with stripline routing in thin dielectrics. Follow it if you like as it will prevent excessive interference with your impedance. However, that distance might not provide the isolation you need. This is one area that can be tested with a field solver by looking at coupled network parameters and crosstalk coefficients between different interconnects.

The above results show the case where the laminates supporting a microstrip or symmetric stripline have Dk = 4.1. What happens if instead we use a lower Dk laminate? Will this affect the results.

Indeed, the results are affected because the capacitance back to the nearby copper pour will be lower. This is because the parasitic capacitance between a trace and the nearby pour is proportional to the dielectric constant in both stripline and microstrip configurations. Therefore, lower parasitic capacitance between these structures would mean we should expect lower impedance deviation for a given trace-to-pour clearance.

The graph below shows more simulation results for the clearance/width ratio, but on a Dk = 3 material (such as RO3003). We can see that a lower clearance/width ratio is allowed near copper pour, including in the case of very thin laminates. These results are supportive of certain designs such as RF systems on thin laminates, as well as HDI designs with fine pitch.

Microstrip stripline ground pour clearance
Calculated clearance-to-width ratio for a PCB laminate with Dk = 3.

I've take a similar approach here to directly calculate expected capacitances to an infinitely large copper pour in another article on parasitic extraction. To learn more about the effects of copper pour near transmission lines that require an impedance specification be achieved, watch the video below. In this video I describe the above points in much more detail, and 


From the above results, it should be very clear that the 3W rule used to determine the ground-to-trace spacing between the microstrip and the nearby ground pour is overly conservative. Note that the above dielectric thicknesses are practical values you might find on a 4-layer or thicker stack-up, depending on the laminate used for stack-up construction. We can also see that, for a given distance to the ground plane clearance, you can have much tighter clearance with a microstrip, whereas a stripline requires much larger clearance in thinner dielectrics. Eventually, when the dielectric gets thick enough, these two curves will converge on each other.

Read Microstrip Ground Clearance Part 2: How Clearance Affects Losses

Determining an appropriate spacing for microstrip ground plane clearance starts with the best PCB stack-up design tools. When you use Altium Designer®, you can easily determine the trace width and spacing required to ensure controlled impedance routing in boards that use grounded copper pour in your PCB layout.

When you’ve finished your design, and you want to release files to your manufacturer, the Altium 365™ platform makes it easy to collaborate and share your projects. We have only scratched the surface of what is possible to do with Altium Designer on Altium 365. You can check the product page for a more in-depth feature description or one of the On-Demand Webinars.

About Author

About Author

Zachariah Peterson has an extensive technical background in academia and industry. He currently provides research, design, and marketing services to companies in the electronics industry. Prior to working in the PCB industry, he taught at Portland State University and conducted research on random laser theory, materials, and stability. His background in scientific research spans topics in nanoparticle lasers, electronic and optoelectronic semiconductor devices, environmental sensors, and stochastics. His work has been published in over a dozen peer-reviewed journals and conference proceedings, and he has written 2500+ technical articles on PCB design for a number of companies. He is a member of IEEE Photonics Society, IEEE Electronics Packaging Society, American Physical Society, and the Printed Circuit Engineering Association (PCEA). He previously served as a voting member on the INCITS Quantum Computing Technical Advisory Committee working on technical standards for quantum electronics, and he currently serves on the IEEE P3186 Working Group focused on Port Interface Representing Photonic Signals Using SPICE-class Circuit Simulators.

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