Modeling Copper Foil Roughness Factor in Altium Designer's Impedance Profiler

Zachariah Peterson
|  Created: June 3, 2020  |  Updated: September 25, 2020
Modeling Copper Foil Roughness in Altium Designer's Impedance Profiler

Advanced transmission line models for long interconnects require that designers include copper foil roughness calculations in order to determine accurate impedance. Without the right models or design software, you’ll be left to estimate the skin effect impedance, dispersion, and parasitics in your PCB. These models can be difficult to work with by hand if you’re not mathematically inclined, but the right design tools can be used to quickly incorporate copper roughness in your impedance profiles as you create your stackup.

With the new layer stack manager in Altium Designer®, you can now include copper foil roughness factors directly in your impedance calculator. This is quite easy to do in the layer stack manager, but it begs the question: what exactly is the copper roughness factor? Which value should be used for your interconnects? This is a complex question that relates to copper deposition processes on cores and laminates. However, with some reasonable approximations in two standard models for copper roughness, you can calculate a reasonable copper roughness factor value in Altium’s impedance profiler.

Impedance Profiles in Your Stackup

The impedance profiler in Altium Designer includes an integrated electromagnetic field solver, which calculates impedance profiles at a desired reference frequency. This solver uses the wideband Debye model, for which accurate model parameters are known up to 10 GHz for microstrips and 20 GHz for striplines (both on FR4). This causal model for the dielectric function of your substrate accounts nicely for dispersion and gives you a very good approximation for your interconnect impedance values throughout your desired bandwidth.

When it comes to modeling resistive and inductive losses due to the skin effect, there are two factors to consider:

  • Interconnect cross-sectional geometry: The cross-sectional dimensions of your traces determine the skin depth for AC signals. This creates resistive and inductive impedance contributions to the characteristic impedance.
  • Surface roughness and morphology of the deposited copper: Real electrodeposited copper is not smooth, and is instead created from accumulated chunks of material. In addition, etching during manufacturing will roughen the surface, which increases losses that would normally occur due to the skin effect.

The first point above can be easily included using the standard equations from electromagnetism. Modeling the second point requires accounting for the internal morphology of the copper trace, as well as the average surface roughness of the trace. If you want to work with the standard circuit model for transmission line impedance, then you’ll use the following equation to include the impedance contributions from copper roughness:

Copper foil roughness and impedance in a PCB transmission line
Real interconnect impedance due to the skin effect and roughness

Roughness correction factors can also be used in a field solver, such as Altium Designer’s integrated field solver from Simberian. The roughness correction factor you use in Altium Designer’s impedance profiler needs to be determined using a causal representation. This can easily be calculated using the Hammerstad or Cannonball-Huray models.

Calculating Copper Foil Roughness Correction Factors

The widely accepted models for calculating roughness correction factors are the Cannonball-Huray and Hammerstad models. The Cannonball-Huray model has more power and adaptability in terms of fitting to experimental data, but its form is more complex. However, enforcing causality in this model does yield a closed-form expression for the roughness correction factor in this model. The main input in the model is a measurement of the average copper particle size in a trace (called a cannonball in this model).

In contrast, the Hammerstad model provides a closed-form equation for the copper roughness correction factor, which is a function of surface roughness. This makes the Hammerstad model easier to work with as your manufacturer only needs to supply an RMS surface roughness value, which can be determined from a simple atomic force microscope (AFM) surface profile measurement.

In both models, the goal is to calculate K, which is then multiplied into R in the following lossy characteristic impedance equation:

PCB transmission line with a copper foil roughness correction factor
Characteristic transmission line impedance with a copper foil roughness correction factor K.

The table below shows the formulas used to calculate K in the above equation.

Copper foil roughness and impedance in a PCB transmission line
Roughness correction factor equations.

I’d like to point designers to a DesignCon 2018 paper for more information on using a related set of formulas for causal copper foil roughness correction factors. Notice that the copper foil roughness correction factors above are functions of frequency, so you will need to choose a limiting frequency value (usually 10 GHz is a good benchmark). Once you’ve calculated this value, you can enter it into the impedance profiler in Altium Designer.

Including Causal Copper Foil Roughness in Altium Designer

Copper foil roughness is quite easy to include in the layer stack manager in Altium Designer. Once you’ve created a blank PCB and you are designing your stackup, simply click on the Impedance tab at the bottom of the layer stack manager. This will bring up the Impedance Profile window, as shown below. In this window, you can input the copper foil roughness parameters for your board, and the electromagnetic field solver will automatically determine the geometry that meets your target impedance within your desired tolerance.

Modeling copper foil surface roughness and a roughness factor in Altium Designer
Example impedance profile calculation in Altium Designer (see lower right for copper roughness parameters).

The impedance profiler will automatically calculate the interconnect impedance for your layer stack and the roughness parameters you entered. You can then save this impedance profile and use it in your design rules. This helps you semi-automate tasks like length tuning/delay tuning, differential pair routing, and signal integrity calculations.

Altium Designer® contains many more layout and routing features for your next advanced design. Once you’ve incorporated copper foil roughness into your stackup, your impedance profile will be accessible by all the other design tools and your high-speed design rules. This is critical for ensuring your next advanced design meets important signaling standards and that interconnect losses are kept in check.

Now you can download a free trial of Altium Designer and learn more about the industry’s best layout, simulation, and production planning tools. Talk to an Altium expert today to learn more.

About Author

About Author

Zachariah Peterson has an extensive technical background in academia and industry. He currently provides research, design, and marketing services to companies in the electronics industry. Prior to working in the PCB industry, he taught at Portland State University and conducted research on random laser theory, materials, and stability. His background in scientific research spans topics in nanoparticle lasers, electronic and optoelectronic semiconductor devices, environmental sensors, and stochastics. His work has been published in over a dozen peer-reviewed journals and conference proceedings, and he has written 2500+ technical articles on PCB design for a number of companies. He is a member of IEEE Photonics Society, IEEE Electronics Packaging Society, American Physical Society, and the Printed Circuit Engineering Association (PCEA). He previously served as a voting member on the INCITS Quantum Computing Technical Advisory Committee working on technical standards for quantum electronics, and he currently serves on the IEEE P3186 Working Group focused on Port Interface Representing Photonic Signals Using SPICE-class Circuit Simulators.

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