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    How to Avoid Common Signal Integrity Issues in Your Designs

    Barrey Olney
    |  February 21, 2017

    Are you doing everything you can to resolve pcb signal integrity issues in your high-speed designs? Read on to find out how to avoid the most types of signal integrity issues with board stackup and routing solutions for Altium Designer®.

    High-performance designs bring their own unique set of challenges in the world of electronic design, and you are not alone in needed assistance with signal integrity!

    The Birth of High-Speed Design

    The increase in high-frequency signal integrity designs is tightly woven with the steadily increasing performance of electronics systems over the years. As system performance increases, the printed circuit board challenges begin to mount. Dies become smaller, board layouts become more densely packed, and we constantly seek chips that provide the lowest possible power consumption. With all these rapid advancements in technology, we have found ourselves at the core of high-speed design including all of its complexity and considerations. No wonder signal integrity is so important!

    Looking Back for Perspective

    Much has changed in PCB design over the past 30 years. In 1987, we thought that 0.5 micron technology was the be-all-end-all, but today we find 22nm technology to be cutting edge. Edge rates in 1985 that were pushing design complexity forward (typically 30ns) now pale in comparison to today’s edge rates (1ns), as shown in the image below:


    Edge rate changes over the past 30 years

    Progress Mired by Problems

    Progress is not without its problems. With increases in system performance and the adoption of high-speed design practices, we have encountered a number of issues that must be handled in the design environment. To summarize these challenges:

    Signal Quality

    The move by IC manufacturers to lower core voltages and higher operating frequencies has led to a sharp rise in edge rates. These edge rates can create reflections and signal quality problems in designs if left unterminated.


    High-signal speed designs, with densely packed traces, often lead to crosstalk – a phenomenon associated with the unintentional electromagnetic frequency coupling between traces on a Printed Boards. 

    Crosstalk can be edge coupled on the same layer, or can be broadside coupled by traces on adjacent layers. The coupling is three-dimensional. Traces routed in parallel and broadside cause greater amounts of crosstalk than those routed side by side.

    Broadside coupling (top) compared to edge coupling (bottom)

    Radiated Emissions

    Faster edge rates in legacy designs, using the same frequency and trace length as before, now produce ringing in the un-terminated transmission line. This leads to radically higher radiated emissions, far exceeding the FCC/CISPR Class B limits for an unterminated transmission lines.

    Radiated emissions from the 10ns edge rate (left) and 1ns (right)

    Design Solutions

    Because signal integrity and power integrity issues tend to manifest themselves as intermittent operation, they may be rather difficult to diagnose. It’s always better to find these issues during the high speed design process, and eliminate them at their source rather than attempting to resolve them at a later stage leading to delayed production. With the help of a stackup planner tool, it becomes much easier to implement solutions for signal integrity issues in your designs.

    Board Stackup Planning

    The absolute first thing to look at in your high-speed design is the board stackup. The substrate is the most critical component of the assembly, and its specifications need to be planned carefully to avoid impedance discontinuities, signal coupling and excessive electromagnetic emissions. When looking at your board stackup, keep these tips and recommendations in mind for your next design:

    • All signal layers should be adjacent to, and closely coupled to, an uninterrupted reference plane, which creates a clear return path and eliminates broadside crosstalk.

    Substrate with each signal layer adjacent to a reference plane

    • There is good planar capacitance to reduce AC impedance at high frequencies. Closely coupled planes reduce AC impedance at the top end and dramatically reduce electromagnetic radiation.
    • High-speed signals should be routed between the planes to reduce radiation.
    • Reducing the dielectric height will result in a large reduction in your crosstalk without having a negative impact on available space on your board.
    • The substrate should accommodate a number of different technologies. For example: 50/100 ohm digital, 40/80 ohm DDR4, 90 ohm USB.

    Routing and Workflows

    After carefully planning your stackup, it’s now time to move onto the routing of your board. With careful configuration of your design rules and workspace, you’ll be well equipped to successfully route your board in the most efficient way possible. Use these tips to make routing your board easier while avoiding unnecessary crosstalk, radiation, and signal quality issues:

    • Simplify your view to easily see split planes and current return paths. To do this, determine which copper plane (either ground or power) that each signal layer is referenced to. Then, turn on that signal layer and plane layer to view them simultaneously. This allows you to easily see traces crossing split planes.

    Adjacent Plane Combined.png

    Multiple signal layers (left) compared with top layer and adjacent plane view (right)

    • If the digital signals must cross a split in the power integrity reference plane, you can place one decoupling capacitor or two (100nF) close to the offending signals to boost the signal integrity. This will provide a path for the return current between the two supplies.
    • Avoid routing traces in parallel and broadside as they cause greater amounts of crosstalk than those routed side-by-side.
    • Keep the parallel trace segments as short as possible to reduce crosstalk, unless you are using a synchronous bus. Space the signal groups such that the address and data spacing are three times the trace width.
    • Take caution when using buildup microstrip layers on the top and bottom of your board. This can lead to crosstalk caused by traces routed on adjacent layers which could jeopardize signal integrity.
    • Always route the clock (or strobe) to the longest delay of the group of signals. This allows the data to settle before it is read by the clock.
    • Routing embedding signals between planes will help to minimize radiated emissions, as well as provide ESD protection, which can greatly help the signal integrity. 

    Signal Clarity

    The complexity of electronics design is undoubtedly going to increase in the future, presenting a new set of challenges for printed circuit board designers to solve. Ensuring that your printed circuit board stackup, impedance, and return current paths are correctly configured, this gives you a stable basis for your design. This compliments the new features for high-speed design in Altium Designer, like xSignals®, by empowering you to implement critical signal matching more precisely with the verification of a 2D field solver.

    What tools are you using for your high-signal speed designs? Check out Altium Designer. 

    Reference: Beyond Design: Signal Integrity 1-3, the PCB Design Magazine.

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