Overview of the Human Body Model in EMC

| Created: June 29, 2023 | Updated: March 16, 2024

The human body model (HBM) is used to define EMC standards for electronics, including withstand voltages during ESD events. The model is a simulation model used to mimic the potential ESD that can occur when the human body touches an electronic device. When ESD occurs, the potential energy stored in accumulated charge on the human body will be released to the circuit, and any protection measures must be able to respond to the resulting overvoltage event.

The HBM does not accurately model every potential ESD source, but it does help understand ESD generated by touch from the human body and provides a standardized qualification approach. Because so many standards use the HBM as a reference against which ESD withstand voltages are defined, it’s important to understand how to design to the requirements defined by this model.

Equivalent Circuit in the HBM

The HBM is meant to phenomenologically describe how an ESD event from the human body could discharge current into a protected circuit. This is done using an RC circuit model, and the specific component values used in the circuit model vary based on the standard being used to describe discharge during an ESD event. These values are used in simulation and measurement to examine how a system or integrated circuit will respond to ESD pulses, and to assess whether protection circuits can withstand specified levels of ESD.

The image below shows a typical test setup used to evaluate circuit protection within the specifications in the HBM as defined in certain industry standards. The test setup primarily consists of a capacitor (C) and resistor (R), which are specified in various standards. The inductor (L) represents the inductance of the interconnect leading from the test waveform generator and the protected DUT. The resulting response at the signal pin is monitored and the device can be tested after exposure to the ESD test waveform to evaluate the effectiveness of the protection circuit.

Human body model — *Example ESD test system with protection diodes applied to a test DUT.*

The table below lists a set of testing standards defining HBM parameters and ESD testing requirements. The resistor and capacitor values in the HBM are typically up to 1.5 kOhms and 100-150 pF, respectively. These parameters condition the test waveform to have the desired rise time and peak current for a given voltage exposure.

Standard	Description and Requirements
JEDEC/ESDA JS-001, Section 4.2	A component-level testing standard for quantifying ESD protection C = 100 pF and R = 1.5 kOhms. Requires 2 kV testing voltage.
DO-160, Section 25	An aerospace testing standard with C = 150 pF and R = 330 Ohms (fast pulses); replaces IEC 801-2, equivalent to ISO-10605. Requires up to 8 kV testing voltage with direct contact or 15 kV testing voltage in air.
IEC 61000-4-2	An aerospace testing standard with C = 150 pF and R = 330 Ohms (fast pulses); equivalent to ISO 10605. Requires up to 8 kV testing voltage with direct contact or 15 kV testing voltage in air.
MIL-STD-883, Method 3015.9	A military testing standard where equipment is tested against using C = 100 pF and R = 1.5 kOhms. Involves progressive testing at 500 V, 1 kV, 2 kV, and 4 kV, etc.
AEC-Q200-002	An automotive testing standard where equipment is tested against using C = 150 pF and R = 2.0 kOhms.

A large resistor value accounts for the resistive characteristics of the human body and effectively slows the pulse discharge to the observed value. While the test waveform might exhibit 1-10 nanosecond rise time, the rate of discharge will vary if the resistor and capacitor values are different. This is quite important if the DUT or the protection circuit are capacitive, which will have to respond differently due to its capacitance being in parallel with the test rig.

The IEC 61000-4-2 standard breaks down immunity levels of an electronic system or product into different classes based on their withstand voltage capability. The determined withstand voltage as found in HBM testing is further broken down into classifications. This can be used to standardize and categorize equipment based on its level of ESD immunity. These classifications are shown below.

Classification	Immunity Requirement
Class 0	<250 V
Class 1A	250 V to <500 V
Class 1B	500 V to <1000 V
Class 1C	1000 V to <2000 V
Class 2	2000 V to <4000 V
Class 3A	4000 V to <8000 V
Class 3B	>8000 V

Withstand Requirements for Components

Some components will list their level of compliance against the peak voltage/current requirements in HBM test waveforms directly in the datasheet. An example from the datasheet for a Texas Instruments RS-232 line driver (PN: SN65C3221E) is shown below. This entry provides a peak withstand voltage capability as tested against an HBM. We can also see the standards compliance listed in this introductory section (in this case, IEC-61000-4-2).

As we can see above, components that will be used in environments where ESD is a danger should state explicitly which standards they aim to comply with, whether this is against a standardized HBM model or some other model (see below). Make sure you size any ESD protection to account for, at minimum using the standardized values given in the HBM test waveform with some applied derating.

What Pulse Waveforms Can Be Expected?

Examples of practical ESD pulse waveforms that would be expected in an ESD test or in the event of a real ESD event can be found in the research literature. One paper from 1993 presented at ISTFA excellent examples of these waveforms. This paper can be accessed for free at the following link:

Kelly, M. A., G. E. Servais, and T. V. Pfaffenbach. "An investigation of human body electrostatic discharge." In International Symposium for Testing and Failure Analysis, pp. 167-167. American Technical Publishers LTD, 1993.

If you examine some of the test data in the above publication, you will see how the standards for ESD testing and withstand requirements relate to the expected current, pulse rise time, and discharge rate as described in the HBM. Some example measured waveforms are shown below; these illustrate the correspondence between various discharge sources and the results determined with testing under the HBM.

HBM test data — *ESD test discharge data from Kelly, Servais, and Pfaffenbach.*

The variation in the peak currents is quite clear. However, we can see that the onset of ESD is a very fast process. What matters here is that the protection mechanism must respond within this time window and thus prevent the rising pulse from transferring energy to the protected circuit. In all cases, even with very high peak voltages that would correspond to IEC-61000-4-2, we see that the ESD pulse reaches its peak current in approximately 1 ns. Any protection mechanism that would be used to protect against ESD must respond within about 1 ns, which demands fast diodes.

Alternatives to the HBM

The HBM is a common model used to simulate ESD generated from the human body. However, the HBM is not the only ESD testing model used in EMC, and it’s important to note that ESD that does not result from the human body might not be accurately modeled using the HBM. These alternative simulation and test models include:

Charged device model (CDM); simulates situations where an electronic device becomes charged and then discharges when it comes into contact with another object.
Machine model (MM); a 200 pF capacitor is used to discharge a specific voltage through a 0 ohm resistor, giving a very fast discharge that is limited by the capacitor’s ESR value.

These model alternative situations where ESD events do not necessarily result from contact with the human body. For example, the effective time constant of the equivalent RC circuit used in these test setups the HBM has a time constant on the order of microseconds, reflecting the slow decay of the test capacitor’s voltage during discharge. These other models are used to standardize potential ESD events from other sources that might result in fast pulses (1-10 ns) with much faster decays to zero.

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About Author

Zachariah Peterson has an extensive technical background in academia and industry. He currently provides research, design, and marketing services to companies in the electronics industry. Prior to working in the PCB industry, he taught at Portland State University and conducted research on random laser theory, materials, and stability. His background in scientific research spans topics in nanoparticle lasers, electronic and optoelectronic semiconductor devices, environmental sensors, and stochastics. His work has been published in over a dozen peer-reviewed journals and conference proceedings, and he has written 2500+ technical articles on PCB design for a number of companies. He is a member of IEEE Photonics Society, IEEE Electronics Packaging Society, American Physical Society, and the Printed Circuit Engineering Association (PCEA). He previously served as a voting member on the INCITS Quantum Computing Technical Advisory Committee working on technical standards for quantum electronics, and he currently serves on the IEEE P3186 Working Group focused on Port Interface Representing Photonic Signals Using SPICE-class Circuit Simulators.