PCB Via Current-Carrying Capacity: How Hot is Too Hot?
One common question from designers, particularly new designers that are learning about industry standards, is current-carrying capacity of conductors in a PCB. Trace and via current-carrying capacity are legitimate design points to focus on when designing a new board that will carry high current. The goal is to keep conductor temperatures below some appropriate limit, which then helps keep components on the board cool.
While the recommended current capacity of traces is well-explored and documented in the IPC 2152 standards, vias in multilayer boards have received much less focus. A few crusaders have been busy investigating the questions around via current-carrying capacity and temperature limits, and how they compare to the temperature of a typical trace carrying the same current. Let’s dig into the current (no pun intended) state of thermal demands on vias in PCBs and how they compare to internal and external PCB traces.
What is the Via Current-Carrying Capacity?
Your traces have specified current-carrying capacity, which can be determined using the copper weight and desired temperature rise using the IPC 2152 nomograph. The goal in sizing traces to ensure your board and components remain within a safe operating temperature. The rules for sizing traces are often applied to sizing vias, yet there may be some reservations by designers regarding a safe via temperature limit. I’ve even seen some novice designers worry about a via melting during operation should the temperature rise too high. While your vias won’t get this hot, it is important to compare the temperature of your vias with the traces and planes to which they are connected.
One might have some intuition that the via, being connected at each end to a hot trace with high current, will have a temperature at least as high as the trace connected to it. This seems to make sense; the connected traces and any nearby planes can get quite hot at high current (low copper weight at ~5-10 A), so wouldn’t heat accumulate in the via? In addition, one might naturally conclude that traces on a surface layer would run cooler than traces in an interior layer; so wouldn’t this cause the via to reach a higher temperature as it passes through the interior of a board? These questions surround important points related to via reliability, particularly for microvias.
In fact, the real situation can run opposite to our intuition. First, traces on the surface layer will run hotter than traces in an internal layer. This is because the thermal conductivity of FR4 (approximately 0.25 W/m⋅K) is an order of magnitude larger than that of air; there are alternative substrate options that provide higher thermal conductivity. This means the substrate acts like a heat sink for conductors that pass through the substrate. This applies to vias as well, and it helps explain why vias tend to run cooler than the traces connected to them.
A recent article Douglas Brooks and Johannes Adam in Signal Integrity Journal contains some experimental measurements of temperature in traces and vias carrying high current. To my knowledge, these measurements provide the first comparison of temperature in traces designed to IPC 2152 standards and a via connected to them. These measurements and results from simulations are shown in the tables below.
Obviously, this is much less than the 0.5 A rule of thumb sometimes seen on forums. Rules of thumb tend to be overly conservative, so it's okay to follow them in most cases. However, if you need to provide high DC current you may do more harm than good if you're carving up planes with excessive numbers of vias. Be mindful of this when choosing the number of vias needed to supply power. If you set a less-conservative limit of 1 A per via, and you need to supply 5 A instantaneously, then 5 large vias with thick plating should be fine, as long as your via temperature does not get too hot near a component. The danger here is not one of high temperature, I would argue it's more one of temperature cycling. If there is repeated cycling between very high and low temperatures, fatigue might eventually set in and lead to via failure.
Here, we can see that thin traces tend to run hotter than the via connected to them, with a temperature difference of only a few °C. This can be attributed to the thermal conductivity differences for the air-exposed trace and the via. In effect, heat is dissipated from the via faster than it is dissipated from the thin trace.
The results presented above show one contradiction to the thermal conductivity argument I mentioned above. When the trace becomes quite wide (200 mils), the trace now runs cooler than the via, although the temperature difference is only a few °C. The heat flux away from the trace depends on the exposed surface area and the thermal conductivity of the surrounding media. In this case, where the wide trace has a large exposed surface area, heat is dissipated faster from the trace than it is from the via. This causes the trace to have a lower equilibrium temperature. This relationship can be nicely summarized as follows:
- When the trace is thin, the via acts like a small heat sink for the trace.
- When the trace is wide, the trace acts like a small heat sink for the via.
There are some other points to consider in this analysis. First, plane layers are not considered, and plane layers will act like a large heat sink, further reducing the temperature of the conductors. Next, alternative substrates with high thermal conductivity (e.g., ceramics or metal-core PCBs) will pull even more heat from conductors, leading to an even lower equilibrium temperature for all conductors.
As long as your PCB traces are sized according to the minimum trace widths specified in the IPC 2152 standard, and your vias have thick enough plating, you most likely won’t have to worry about temperature rise in your vias. The excess heat in the interior of the via gets dissipated into the substrate and the nearby traces. In the case where the traces are very wide, they have a larger surface through which to dissipate heat compared to the via. In this case, the heat leaves the trace at a faster rate than it leaves the via, thus the trace will reach a lower equilibrium temperature. This was confirmed in the experimental study by Douglas Brooks and Johannes Adam in SIJ.
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