PCIe Layout and Routing Guidelines

Zachariah Peterson
|  Created: April 1, 2019  |  Updated: January 13, 2021
PCIe Layout and Routing Guidelines

Opening up a computer as a kid and staring at the complicated mess of card slots, chips, and other electronics on a motherboard always made me wonder how anyone could keep all the details about PCB layout straight. Learning more about PCB design for computer architecture and peripherals made me appreciate the dedication PCB designers have for building great electronic devices.

Modern GPU, USB, audio, and networking cards can all run on the back of the same interconnect standard: PCI Express. If you’re new to high speed PCB design for PCIe devices, information on the topic is a bit fragmented unless you purchase a standards document from PCI-SIG (Peripheral Component Interconnect Special Interest Group). Fortunately, the basic specifications can be broken down into some actionable design rules, and you can easily layout and route your next PCIe device using the right PCB design software.

As with any high speed design, blindly following a standard does on routing specs does not guarantee your design will work as intended. Any prototype design should be tested thoroughly to ensure signal integrity problems are not lurking in the design. Even if you've designed everything to the right routing specifications in terms of impedance, trace length, etc., it's still possible for the design to fail due to poor layout choices. PCIe specs for each generation also include testing requirements, which are published on the PCI-SIG website. We won't get into testing here, but keep reading to see a short summary of what's in the standard and how you can design PCIe cards to best comply with newer PCIe generations.

Routing Specifications

Currently, there are five PCIe generations released by PCI-SIG, the industry working group that oversees the PCIe specification. PCIe Gen 5 was released this year, and PCIe Gen 6 devices are expected in 2022. The exact routing specifications depend on which PCIe generation you'll use for your particular components. In terms of design, you'll need to pair up components and host controllers that will support the data rate your components need. PCIe is forward and backward compatible, so the minimum data bandwidth is limited to the minimum of the controller and peripheral components.

Topology and Data Rate

All PCIe links are composed of multiple lanes (groups of differential pairs) that provide high throughput as a group of serial interfaces. Note that, although a PCIe lane is serial, the lanes taken together appear to form a parallel bus, but this is not the case. Communication is bidirectional with groups of Rx and Tx lanes. PCIe lanes are routed point-to-point as differential pairs, so standard rules on length matching and skew should be in place. The PCIe standards define up to 16 available lanes, which also define the size of standardized PCIe card slots. Different host controllers will have different numbers of lanes available, which can then define how many peripherals they can support. PCIe devices use embedded clocking with different line codes (8b/10b in Gen 1 and 2, 128b/130b in Gen 3 and higher), so we don't need to worry about routing an additional clock channel like in DDR. Finally, each generation doubles data throughput from the previous generation, reaching up to 32 GT/s in PCI Gen 5.

Loss Budget and Differential Impedance

The five current PCIe generations have varying specifications on impedance and loss budgets for different generations, and these should be closely followed to maintain required performance. These are summarized in the table below. Some guides on routing will define a trace length maximum, either as a hard number or as a range. I've compiled total loss budgets in the table below; these values are taken at the maximum data rate specified for each generation. Note that these budgets are inclusive of insertion, return, connector, and dielectric/roughness losses along the length of a PCIe lane.


Insertion Loss Budget

Differential Impedance


12 dB @ 2.5 GHz

100 Ohms


12 dB @ 5 GHz

100 Ohms


24.5 dB

100 Ohms or 85 Ohms


26 dB

85 Ohms


32 dB

85 Ohms


32 dB

85 Ohms

Although high speed standards define things like trace lengths in specifications, what's more important is losses along the routing path. All losses from reflections, impedance discontinuities, absorption, copper roughness, and other sources add up throughout the routing path and need to be considered when determining trace lengths. For PCIe, once Gen4 came out, FR4 was no longer the best option and lower loss laminates are needed to support routing over the distances you would see in a rackmount unit or motherboard. Be careful with just taking a trace length calculation for one substrate and extending it to a different substrate as the return and insertion loss spectra for PCIe lanes on the two different substrates are unlikely to match.

PCIe riser extenders plugged into a motherboard

AC Coupling Caps

The current PCIe Base Specification calls for calls for 176 to 265 nF AC coupling caps placed near the transmitter end of a channel to remove DC offset in a PCIe lane. The AC coupling capacitors are required on both sides of a differential pair, and these are placed as a pair of discrete capacitors at the Tx end of a lane (usually 0402 caps). Pay attention to your component datasheet as your driver (host) may recommend a specific value that falls outside the range in the base spec.

Once we get to PCIe Gen6, PAM4 signaling will give another doubling of data rate up to 64 GT/s. Similarly, we'll have another increase in allowed loss value following the trend in the table above. Aside from channel losses and ensuring impedance matching throughout interconnects, stackup design and component placement are two important points to ensure impedance control is maintained for differential pairs in PCIe lanes while enabling routing with minimal layer transitions and interference with other components.

How Stackup and Layout Affect Routing

Typical PCIe boards with lower lane count can use a 4 layer stackup with two interior power planes and two signal layers on each outer surface (microstrip routing, Tx and Rx routed on different sides of the board). Each power layer can be brought to different bias levels, depending on the device requirements. Some designs might use a 6 layer stackup with lower speed signals running between the two power layers; be careful with this as high speed signals on the internal layers can create crosstalk and grounding is needed in these boards. Some guidelines are also available for 8 layer and 10 layer stackups for PCIe boards.

If you're designing a standard PCIe card, you’ll need to make sure that the overall thickness of the board matches the standard 1.57 mm (1 mm for PCIe Mini) thickness and pinout for PCIe cards, regardless of the PCB layer stackup. Other boards with all PCIe components on the same substrate (no edge connector) can have any number of layers or thickness, although stick to standard thickness to ensure reasonable manufacturing costs.

Motherboards with PCIe card slots normally route all signals on the same layer (Rx and Tx on opposite board sides), so you should leave enough room on the board for routing your lanes without layer transitions (more on vias below). If you look at some PCIe routing in later generations, the traces use zig-zag routing to compensate for skew from the fiber weave in the substrate. If you're using a tight glass weave substrate with low losses, you might be able to relax this requirement, but you should still test your board to ensure it is operating within specs for your application.

Traces routed on a PCB with blue solder mask

Pins, Pads, Vias, and Breakout Routing

Routing around obstacles and accommodating components and vias on a PCIe board is especially important. Routing to pins, pads, components, and BGA breakout routing should be symmetric and length matched, with length tuning/mismatch applied near the source end of a link. Differential pairs should be tightly coupled throughout their entire length, so try to avoid variations due to pads, vias, or components along the routing path. This important point in floorplanning can prevent signal integrity problems after a board spin.

The same applies to routing breakouts from a BGA or other components. Routing to a BGA, for example, will require a bend be placed in one trace to reach one of the pads. The same bend should appear in the other trace if possible. The pair should also be routed together between neighboring pads on a BGA, rather than routing with pads between the traces. Take a look at this post on routing into a PCIe interface on a BGA for more information.

For vias, the original draft of the PCIe Gen1 standard from Intel did specify limits on via counts on PCIe lanes, but a strict via count is less important than the total losses from all vias on an interconnect. Although generally everything in PCIe routing happens on a single layer (Tx and Rx on different sides), pay attention to losses when vias are present at the ends of PCIe lanes. Via counts should be ideally minimized and backdrilled (no need to use blind/buried vias), and if you do your layout/routing properly you won't need vias for repeated layer transitions.

Keeping impedance, coupling, and length of your traces within spec is much easier when your PCB design software includes controlled impedance routing features. You can specify the impedance tolerance directly in your design software, and your interactive routing tool will ensure that your traces are laid out with the right geometry and spacing. The layout and routing features in Altium Designer®, are integrated into a single program alongside simulation, verification, and production preparation features. The CircuitStudio® package helps you ensure that your design meets PCIe layout routing specifications.

Now you can download a free trial of Altium Designer and learn more about the layout, routing, and verification features. Talk to an Altium Designer expert today to learn more.

About Author

About Author

Zachariah Peterson has an extensive technical background in academia and industry. He currently provides research, design, and marketing services to companies in the electronics industry. Prior to working in the PCB industry, he taught at Portland State University and conducted research on random laser theory, materials, and stability. His background in scientific research spans topics in nanoparticle lasers, electronic and optoelectronic semiconductor devices, environmental sensors, and stochastics. His work has been published in over a dozen peer-reviewed journals and conference proceedings, and he has written 2500+ technical articles on PCB design for a number of companies. He is a member of IEEE Photonics Society, IEEE Electronics Packaging Society, American Physical Society, and the Printed Circuit Engineering Association (PCEA). He previously served as a voting member on the INCITS Quantum Computing Technical Advisory Committee working on technical standards for quantum electronics, and he currently serves on the IEEE P3186 Working Group focused on Port Interface Representing Photonic Signals Using SPICE-class Circuit Simulators.

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