PCB Sub-Laminations With Mechanically-Drilled Vias

Zachariah Peterson
|  Created: August 2, 2025  |  Updated: September 12, 2025
PCB Sub-Laminations With Mechanically-Drilled Vias

When most designers find out they need blind vias, they probably default to an HDI design with laser-drilled vias and a sequential lamination process. However, that is not the only way to use blind vias. Both blind and buried vias can be mechanically drilled to provide routing on multiple layers without exposing via landing pads on both sides of the PCB. However, mechanically drilled blind and buried vias have rules which are different from the standard through-hole process and from HDI designs.

Fabrication of a PCB stackup with mechanically drilled blind and buried vias relies on constructing multiple laminations which are bonded together and plated to form the stackup. A series of stack-drill-plate steps are used to form each of the laminations and bond them together into the complete PCB stackup. These cycles in the fabrication process can place unanticipated constraints on the PCB designer. I will discuss these aspects of blind and buried via fabrication in this article.

Counting Sub-Laminations in a PCB Stackup

An understanding of constructing stackups with multiple sub-laminations and mechanically drilled blind/buried vias is quite important as it relies on getting the layer arrangement and via spans correct. If these are not calculated correctly or verified with a fabrication house, the result can be extensive redesigns. In addition, only certain via span placements will be allowed in sub-laminations, and this will affect your choice of routing layers and the overall fabrication steps. Finally, the fabrication process alters your copper plating, which will change the design rules and potentially create defects.

First, we need to know how to count sub-laminations in a stackup. As an example, consider the conventional stackup with blind and buried via transitions shown below.

Here we have the following list of sub-laminations:

  • One lamination: layers 1 through 3 / layers 16 through 14
  • One lamination: layers 1 through 5 / layers 16 through 12
  • One lamination: layers 16 through 9
  • One lamination: layers 6 through 8

NOTE: The 6-8, 16-14, and 16-12 via spans will require approval from your fabricator due to the arrangement of cores and prepregs. Your fabrication house will need to approve the core-prepreg arrangement because prepregs are required to bond each sub-lamination together. To get around this, we often prefer to connect only even numbers of layers with blind or buried vias.

In total, we have four sub-laminations, which are then pressed together with pre-pregs to form the final stackup. Through-hole vias are then applied after the final pressing step.

During this process, layer 16 is exposed to three plating cycles while layer 1 is exposed to two plating cycles. Layers 6 and 8 are each exposed to one plating cycle. Each plating cycle adds thickness to the base copper foil. If the resulting copper distribution becomes asymmetric, there is the potential for warpage when the sub-laminations are pressed together to form the final stackup. I will discuss this more in the section on design rules below.

PCB Stackup Fabrication Process with Multiple Sub-Laminations

PCB stackups with mechanically drilled blind and buried vias go through a particular fabrication process requiring multiple drilling and plating steps. The process for building the stackup with these vias proceeds as shown in the graphic below.

In this stack-drill-plate process, multiple rounds of plating can cause large copper thicknesses to accumulate on some layers. This will be the case for each lamination cycle that occurs during the stackup fabrication process. So, if you can count the number of sub-laminations, you can predict the final plating thickness that will appear on various layers.

In the example in the previous section, suppose we start with a base copper foil weight of 0.5 oz./sq. ft. If we start with this base copper weight and we plate by an additional 0.5 oz. during each lamination cycle, the final plated copper weight on each of the layers will be:

1

2 oz./sq. ft.

2

0.5 oz./sq. ft.

3

1 oz./sq. ft.

4

0.5 oz./sq. ft.

5

0.5 oz./sq. ft.

6

1 oz./sq. ft.

7

0.5 oz./sq. ft.

8

1 oz./sq. ft.

9

1 oz./sq. ft.

10

0.5 oz./sq. ft.

11

0.5 oz./sq. ft.

12

1 oz./sq. ft.

13

0.5 oz./sq. ft.

14

1 oz./sq. ft.

15

0.5 oz./sq. ft.

16

2.5 oz./sq. ft.

It should be quite clear that the asymmetric arrangement of blind and buried vias also produces an asymmetric arrangement of copper weights in the PCB stackup. While this could conceivably be addressed by starting with different copper weights on different layers, that will impact your unit cost, and it is not always possible to get a perfectly symmetric distribution of copper with this method. Instead, we would prefer symmetric arrangements of blind and buried vias to help keep the copper weight symmetric in the final stackup.

PCB Design Rules with Multiple Sub-Laminations

The final points to discuss relate to how using sub-laminations with mechanically drilled blind and buried vias impacts your PCB design rules and constraints. First, we have some important constraints on the selection of layer spans for blind and buried vias.

  1. Start and end rule - A mechanically drilled blind/buried via span may not end on the same layer as the start of a different mechanically drilled via span. The exception is if sequential lamination is used, or you will need laser-drilled blind vias, which would allow stacking.
  2. No crossing vias - Mechanically drilled blind/buried via spans may not cross over each other, but the via spans can be nested.
  3. Prepreg bonding - When bonding sub-laminations, the sub-stacks can only be bonded together with prepregs, not with cores.

The “crossing vias” rule can be a bit confusing, particularly when looking at buried vias. While overlapping spans are not manufacturable, nested spans are manufacturable, which I show in the graphic below.

The final remark I will make relates to different via spans which start and end on the same layer. Due to this limitation from the manufacturing process, we cannot use the typical blind/buried via structure one would see in an HDI PCB. This may require using a blind via and a through-hole via to reach all the way across the PCB. This may not be desirable for some signals, such as very high-speed signals that demand stub removal. Consider steps like back drilling where necessary, and plan those important routes carefully.

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About Author

About Author

Zachariah Peterson has an extensive technical background in academia and industry. He currently provides research, design, and marketing services to companies in the electronics industry. Prior to working in the PCB industry, he taught at Portland State University and conducted research on random laser theory, materials, and stability. His background in scientific research spans topics in nanoparticle lasers, electronic and optoelectronic semiconductor devices, environmental sensors, and stochastics. His work has been published in over a dozen peer-reviewed journals and conference proceedings, and he has written 2500+ technical articles on PCB design for a number of companies. He is a member of IEEE Photonics Society, IEEE Electronics Packaging Society, American Physical Society, and the Printed Circuit Engineering Association (PCEA). He previously served as a voting member on the INCITS Quantum Computing Technical Advisory Committee working on technical standards for quantum electronics, and he currently serves on the IEEE P3186 Working Group focused on Port Interface Representing Photonic Signals Using SPICE-class Circuit Simulators.

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