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Microvia Technology and Beyond for HDI Design

Zachariah Peterson
|  Created: May 27, 2019  |  Updated: September 25, 2020
Microvia Technology and Beyond for HDI Design


If you have ever opened up the case on a broken smartwatch or smartphone, then you know the amount of functionality that is packed into such a small device. Enter microvia technology. Shrinking via structures have facilitated high density interconnect layout and routing in PCBs, allowing ever more functionality to be packed into small footprints.

As consumers continue to demand more functionality on individual devices, with further scaling hindered by quantum tunneling, PCB designers have a role to play in decreasing device form factors and packing more functionality into a single package. What new multilayer routing architectures will arise from these efforts?

From Through-Hole to ELIC

When working with a small number of layers and a relatively thin board, you can usually get away with through-hole vias. At some point, you’ll be routing so many connections over a small area that you will need unique ways to reach the inner layers of your board while still conserving valuable board space. Through-hole vias don’t allow multiple signals to be routed through a given interior layer area. As the number of layers in your board increases, through-hole vias will still only allow you to route signals between two layers.

Even if through-hole via size approaches microvia sizes, it will still not solve the problem of taking up unnecessary interior board space. Buried vias help the situation somewhat, although they still take up a decent amount of board space if you have to route between layers that are not adjacent. This is where microvias give you significantly more flexibility.

Microvias were originally used to route signals between adjacent board layers when the via holes were too small to place with a drill bit. Instead, a laser places these vias in a single layer of a PCB, while the board is created using sequential buildup (SBU). Note that we also use SBU to place traditionally drilled blind and buried vias in a layer stack, but microvias are simply  laser-placed and plated using a tailored electrolytic deposition process.

Just like drilled vias, microvias come in the blind and buried variety, but they only span a single layer. If you need to span across multiple layers, you can use stacked microvias or skip vias to route the desired connections. Some manufacturers estimate that using microvias for HDI reduces the total board space occupied by vias by 60% to 70%. This leaves more room for routing signal in the interior of your board. Creative use of microvias also allows you to reduce layer counts.

Integrated circuits on a green PCB

Microvias used for BGA escape routing

Microvias are really a necessity when placing components with high pin densities. As pin densities continually increase, we need to place more microvias directly onto mounting pads. We also fill and plate these laser-drilled microvias to prevent solder from wicking into the via and forming a weak electrical connection.

Beyond Microvia Technology: Next Generation HDI Routing

One recent innovation in this area is the development of every-layer interconnect (ELIC) routing. GPUs, CPUs, memories, and other BGA-mounted devices with extremely fine pitch routinely use ELIC. This via architecture facilitates connections throughout the interior of a board without the need for a core in the center of the board. This architecture essentially uses stacked, copper-filled microvias to connect the layers of the board.

Increasing routing and layout density even further will require new architectures for routing between layers in a multilayer PCB. The most promising innovation for this is vertical conductive structures, or VeCS. This unique multilayer PCB architecture allows for a larger number of tracks between BGA pads compared to dog bone fanouts or via-in-pad. For a given board and component arrangement, this type of routing architecture can decrease dependence on multiple interior signal layers for HDI routing.

The VeCS architecture is not cylindrical. Instead, a copper-plated groove routes into the board surface. A slightly wider drill punches holes along the groove, leaving behind straight vertical conductors that pass through the inner layers. VeCS doesn’t require any other specialized manufacturing techniques or tooling, and it can provide the same functionality as ELIC.

HDI routing for a CPU with microvia technology

Keeping up with microvia technology and newer innovations in HDI routing takes design software with a full suite of mechanical and electrical design tools in a single package. Altium Designer is the only PCB design software platform that contains the best schematic design, routing and layout, signal analysis, and deliverable generation tools in a single interface. You can generate the deliverables your manufacturer needs to fabricate new routing architectures for HDI PCBs.

Download a free trial of Altium Designer today to learn more about the industry’s best design, simulation, and verification features. Talk to an Altium expert today to learn more.

About Author

About Author

Zachariah Peterson has an extensive technical background in academia and industry. He currently provides research, design, and marketing services to companies in the electronics industry. Prior to working in the PCB industry, he taught at Portland State University and conducted research on random laser theory, materials, and stability. His background in scientific research spans topics in nanoparticle lasers, electronic and optoelectronic semiconductor devices, environmental sensors, and stochastics. His work has been published in over a dozen peer-reviewed journals and conference proceedings, and he has written 2500+ technical articles on PCB design for a number of companies. He is a member of IEEE Photonics Society, IEEE Electronics Packaging Society, American Physical Society, and the Printed Circuit Engineering Association (PCEA). He previously served as a voting member on the INCITS Quantum Computing Technical Advisory Committee working on technical standards for quantum electronics, and he currently serves on the IEEE P3186 Working Group focused on Port Interface Representing Photonic Signals Using SPICE-class Circuit Simulators.

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