Revisiting Vertical Connection Structures-VECS Part 2

It’s been about one year since I posted a BLOG about the new VeCS Technology (vertical connection structures) invented by Joan Tourné. Since then, Joan has written four papers detailing much more information about his invention. This is a quick update, in case you have not seen or read those papers. He has two more coming up in January 2020, and March 2020 in PCB007.

Vertical Conductive Structures-Rethinking Sequential Lamination [1]

NEXTGIN Technology, of which Joan Tourné is the founder and CEO, is publishing six articles detailing their new technology, VeCS, which I introduced in a BLOG a year ago. This was their first article, and focused on “rethinking” how we build High Density Multilayers (HDI). In particular, plating aspect ratios and sequential lamination.

Their VeCS technology replaces the small TH and blind via with slots. The article details the field plating tests of through-slots and blind-slots (Fig.1a), and how they can be plated in conventional, high-throw acid copper baths. In particular, the blind slots can be plated with an aspect ratio (AR) of up to 4:1. Graphs and cross-sections show the results of their tests. (Fig. 1b)

The other cost driver in HDI is the sequential lamination. VeCS can create and plate variable depth drill/routed slots so that a very high-density multilayer can be created with just a singe lamination, as seen in Figure 1c and 1d.

Vertical Conductive Structures-VeCS and Micro-machining [2]

The second article details more about the creation—and what Nextgen calls-micro-machining—of the critical slot. Although conventional drill or router bits can be used, they have had better results with a newer bit from HPTec in reducing drill ‘wander’. Eight cross-sections and diagrams illustrate the unique nature of the blind slot that featured in Fig. 1d. Critical dimensions are seen in Figure 2.

Vertical Conductive Structures-Design Tool Techniques [3]

Part 3 was a longer article as it covered the critical elements of designing a VeCS multilayer. Although the author’s text and data used Cadence Allegro 17.2, I’m sure one of the readers of this BLOG can submit the equivalent procedure in Altium Designers 19 or 20.

The manufacturing process was outlined in my first BLOG, and designing VeCS is not much different from designing complex TH or HDI multilayers. Overlapping of images (annular ring), slot to copper, second route to slot, etc., are important to have the correct setup. Currently, there are two “slot” technologies; VeCS-1, where the slots go through the board, and VeCS-2, where we do multi-level blind slots (Fig. 3a).

The critical design procedures detailed in the article are:

• Setting up VeCS design rules(see Fig. 3b)
• Pad definitions: innerlayers (Fig. 3c); outerlayers (Fig. 3d)
• Pad stack generation (Fig. 3e)
• Plated slots structures and dimensions
• Non-plated holes/slot (Slot Separator)
• Connection vias
• Finalized Mechanical symbols
• VeCS structures
• Changing layer depth (VeCS-2)
• Pin properties
• Fabrication output

Vertical Conductive Structures-Tuning Your Signal Performance [4]

The last article (Part-4), currently published on VeCS, shows the procedures for signal routings and the improved performance with VeCS. Single-ended signals and differential-pairs were routed with their reference planes on an eight-layer VeCS-2 multilayer with isometric views of trace terminations. 

Simulations for signal integrity were run to see the TDR response as a function of the variable signal rise-times. A 95-ohm differential impedance was shown with and without VeCS tuning by table and bit patterns, for both launch and exit eye patterns.

Figure 4 highlights the upcoming Part-5 article in January, covering reliability testing of VeCS and the results (disclosed in the HDPUG report of VeCS coupons) achieving 10-30 cycles, as compared to through-holes of 7-10 cycles.

Would you like to find out more about how Altium can help you with your next PCB design? Talk to an expert at Altium.

References

1.  Tourné, Joan, Vertical Conductive Structures- Part1: Rethinking Sequential Lamination, PCB007 magazine, pp88-93, April 2019
2.  Tourné, Joan, Vertical Conductive Structures-VeCS and Micro-machining, PCB007 magazine, pp72-78, June 2019
3.  Tourné, Joan, Vertical Conductive Structures-Design Tool Techniques, PCB007 magazine, pp90-99, August 2019
4.  Tourné, Joan, Vertical Conductive Structures-Tuning Your Signal Performance, PCB007 magazine, pp68-76, October 2019