Routing Topology Configuration in PCB Design for Power, Data, and Peripherals

When I was young, I would open up old computers and marvel at how the electronics were interconnected. Back then, SCSI hard drives were daisy-chained using multi-connector ribbon cables, a common practice in PCB design. Over the years, PCB design has evolved significantly, with modern computers now incorporating advanced digital interfaces on PCBs and between boards in larger systems, drawing from standard networking topologies. Although PCB form factors have changed, the fundamental structure of electrical connections between components and subsystems in electronic products has remained consistent.

If you're a new designer who is just getting started with an advanced interface like DDR, or you're daisy chain routing your first bus protocol, it's important to understand some basics about PCB routing topology. There's also the matter of designing power distribution, which can have its routing protocol for power buses, connections between boards, and ensuring consistent ground in your system. 

Common Routing Topology for Your PCB

Several common PCB routing topologies are used throughout PCBs for routing power, digital data, and even some specialty analog systems. Some advanced topologies are used for computer peripherals like memories. The common routing topology in most PCBs has the same names as their networking topology analogs, so familiarity in these areas helps. Unlike networking, the goal of implementing a routing topology configuration in PCB design is not limited to data transmission between components. Power is also "routed" around a system in a definite PCB topology, and different topologies may be selected for various reasons.

The image below summarizes the common networking topologies, some of which might be used in various areas of PCB design.

Each of the boxes in this image could be a single component on a board, a circuit block on a board that contains multiple components, or a single board in a multi-board system. As we zoom out to higher levels of abstraction, we start to see how these topologies start to resemble standard networking topologies. At the granular level, where we're looking at individual components, only some of these topologies are practical at the board level. The table below summarizes how these various topologies are implemented on the PCB, or at the system level between multiple boards.

Some commentary is useful here as it shows where each PCB topology might be useful and how they are practically used for different portions of a system.

Star routing can be used to provide multiple ground connections to a single point for power distribution. The star routing topology is also used with a system clock in a high-speed PCB, as is evident in the image of the BGA below. The signal originates from a single point and is routed to different components on the board as needed. Note that the terms “source single point” and “star” are two different names for the same PCB topology. The difference with a star routing topology is that this source point is placed at the center of the downstream components.

Tree routing (or multi-point) applies the same idea to multiple "stars" in a hierarchy, where multiple power rails are broken out from a single point and sent to different circuit blocks or devices. Another variation is source multipoint topology, where a single power rail is used as a bus and supplies power to downstream circuit blocks.

Some variations on the topologies in the above table are used for more advanced digital protocols. Two important examples are DDR2 and higher, as well as PCIe.

Routing Topology for Memories and Computer Peripherals

When it comes to memory modules and their interface with a processor, combinations of more complex topologies connect devices within a board. The simple point-to-point topology is also used for advanced protocols like PCIe. Let's look at these examples as they illustrate how standard routing topology is adapted to advanced signaling standards.

T-Topology

The T-topology is commonly used in DDR2 and earlier versions of DDR3 memory. This topology combines tree and point-to-point network routing. Command, clock, and address traces are routed in a tree structure, while data lines are routed point-to-point directly to the processor. Although this topology helped achieve higher data rates, the number of usable memory modules and overall data transfer rates were limited by capacitive loading.

Fly-by Topology

Newer DDR memory modules use fly-by topology. The primary PCB topology used in DD3 and DDR4 represents a combination between a point-to-point network and a bus network. Power/ground, command, clock, and address signals are routed on a bus to each DRAM/SDRAM, and these are then routed to a processor using differential pairs. This is a significant upgrade compared to DDR2 and earlier memories. Compared to T-topology, fly-by topology supports operation at higher data rates while reducing timing skew between heavily loaded signals traveling from the processor to memory modules.

Newer memory architectures, such as NAND flash memory with 3D Xpoint from Intel, have an internal crossbar-type topology inside the package. Still, manufacturers will recommend a point-to-point topology for the actual layout of a PCB topology. However, star and T-topologies can also be used with NAND flash packages. Using a point-to-point topology with NAND flash packages is simple enough that a low-cost four-layer stack-up can be used. In this case, ground and power are placed on the internal layers, and signals are routed on the surface layers.

Point-to-Point Routing for PCIe

PCIe is a bidirectional serial protocol that uses a point-to-point routing topology between peripherals, where components are cascaded along an interconnect. In some ways, PCIe appears as a parallel bus architecture, but this is not really the case as different lanes in PCIe buses are not broken out into different devices. PCIe lanes use impedance-controlled differential pair routing with separate Tx and Rx lanes.

The lengths of pairs in PCIe's point-to-point topology don't need to be the same. In other words, the length of the RX pair can be different from the TX pair, and vice versa, as long as the traces that make up a pair are length-matched. To learn more about the important technical points for PCIe interconnect design, take a look at the following resources:

• PCIe Layout and Routing Guidelines
• What Happens to PCIe Signals Traversing Blind Vias at Higher Speeds?
• What Goes into PCIe 5.0 Layout and Routing?

Technology is continuously advancing, especially in computer peripherals and memory devices. This means engineers and systems designers need ever more powerful tools to keep up with the pace of new developments. Altium Designer^® integrates layout and routing features into a single program alongside verification, simulation, and production preparation tools. You’ll have the advanced tools you need to implement routing topology configuration in PCB topology design for any application.

When you’ve finished your design, and you want to release files to your manufacturer, the Altium 365^™ platform makes it easy to collaborate and share your projects. We have only scratched the surface of what is possible to do with Altium Designer on Altium 365. You can check the product page or one of the On-Demand Webinars for a more in-depth feature description and information on routing topology configuration in PCB Design.