Routing Topologies in Your PCB and Computer Peripherals
If you were to look inside a modern electronic product, you might wonder how everything inside is linked together. Conductors running between components play a central role, but how are components grouped together? How do different components link back to power and ground? The answer lies in the topology implemented during the design phase.
If you remember those old SCSI hard drives in 1990’s computers, then you are already familiar with daisy chain topology where data is sent to drives in series. Newer PCBs for computer peripherals and memories use more complicated routing topologies that provide faster data transfer, faster slew rate, better signal integrity, and/or prevent timing skew within signal nets.
Common Routing Topologies
Several common routing topologies are used throughout PCBs and advanced topologies for computer peripherals. Star routing is normally used to provide multiple ground connections to a single point, which suppresses ground loops. The star topology is best used with a system clock in a high-speed PCB. The signal originates from a single point and is routed to different components on the board as needed.
The same idea can apply to supplying power to multiple components, where power rails are broken out from a single point and sent to different devices. Another idea is to use source multipoint topology, where a single power rail is used as a bus and supplies power to downstream ICs. With signals, bus routing can be used with nets that need to be sent from one upstream component to multiple downstream components.
The terms “source single point” and “star” are two different names for the same topology. In both cases, a signal, power point, or ground point is placed at a single location, and traces are routed outward to their destination. The difference with a star topology is that this source point is placed at the center of the downstream components. When dealing with signals, be sure to pay attention to fanout values from the source point.
Routing Topologies for Memories
When it comes to memory modules and their interface with a CPU, combinations of more complex topologies connect devices within a board. These topologies for memories are combinations of simpler topologies that are used in other PCBs.
The T-topology is used in DDR2, earlier memories, and is a combination of a tree and point-to-point network. The command, clock, and address traces are routed in a tree-type network, while data lines are routed in a point-to-point manner directly with a processor. While this topology was useful for taking advantage of greater data rates, the number of usable memory modules and data transfer rates were limited by capacitive loading.
Newer memory modules use fly-by topology. The primary topology used in DD3 and DDR4 represents a combination between a point-to-point network and a bus network. Power/ground, command, clock, and address signals are routed on a bus to each DRAM/SDRAM, and these are then routed to a processor using differential pairs. This is a significant upgrade compared to DDR2 and earlier memories.
Compared to T-topology, fly-by topology supports operation at higher data rates while reducing timing skew between heavily loaded signals travelling from the processor to memory modules. Simultaneous switching noise can also be reduced by creating timing skew between the address lines and point-to-point signal nets that carry data.
Newer memory architectures, such as NAND flash memory with 3D Xpoint from Intel, have an internal crossbar-type topology inside the package. Still, manufacturers will recommend a point-to-point topology for actual layout on a PCB. However, star and T-topologies can also be used with NAND flash packages. Using a point-to-point topology with NAND flash packages is simple enough that a low-cost four-layer stackup can be used. In this case, ground and power are placed on the internal layers, and signals are routed on the surface layers.
Point-to-Point Routing for PCIe
Following the common trend for modern computer architecture, PCIe also uses a point-to-point routing topology. A PCIe link is formed when common mode differential pairs are routed from upstream Tx (Rx) connections to the downstream Rx (Tx) connections. The endpoints in this topology are terminated at 100 Ohms, matching the impedance of the common-mode differential pair signal lines routed throughout the network.
Some design allowances in the PCIe routing guidelines might seem to defy conventional high-speed routing guidelines. One finds that the limitations on trace lengths for differential pairs ensure that signals routed along a point-to-point topology are designed to ensure signal synchronization across the network.
The length of the two pairs in the PCIe point-to-point topology doesn’t need to be the same. In other words, the RX pair can be much longer than the TX pair, and vice versa. That means that if you place your AC caps on the bottom for both TX and RX, you can route the TX pair around the RX pair, meaning your vias can be placed directly at the connector.
In point-to-point routing for PCIe devices, ground vias should be placed symmetrically on either side of a differential pair that changes layers, as this allows return currents to be induced and travel to the reference planes. This should be done regardless of the number of layers appearing in the stackup for a PCIe device.
Technology is continuously advancing, especially in computer peripherals and memory devices. This means engineers and systems designers need ever more powerful tools to keep up with the pace of new developments. Altium Designer® integrates layout and routing features into a single program alongside verification, simulation, and production preparation tools. You’ll be able to implement routing topologies for any application.