Vias 101 Part 2
In this second “Vias 101” article, we will be continuing on from our previous discussion of essential via parameters. This time we will examine aspects of via placement, problems with via placement leading to plane voiding, and finally looking at some unique use cases of vias termed transfer vias and stitching vias.
Keep in mind that there are far more parameters and details to vias in PCB design than we will be covering in this short article. However, the article will provide beginner PCB design engineers with a good starting point to be able to delve deeper into the topic. Let’s get started!
Regardless of if we are dealing with traces, components, outlines, vias, and so on, we always need to think about clearances between these elements, such as between vias and traces, vias and vias, vias and pads, and so on. As usual, minimum clearances are detailed by your chosen PCB manufacturer or standard. However, I would advise you to stay away from these minimums, not only for manufacturing reasons but also for other reasons such as cross-talk.
Additionally, when we are looking at power and ground vias, we want their connections to relevant component pads to be as short and as wide as possible to minimise inductances. This doesn’t mean placing the vias in or directly adjacent to any pad but a reasonable distance away so that you don’t get problems with solder wicking.
As vias come in pairs, we want to typically place power and ground vias close together to minimise inductance, and improve power delivery characteristics.
When spacing vias closely to one-another we get an issue known as voiding. Essentially, for through via (vias that go through the whole thickness of the PCB), placing vias close to each other can cause cuts in the reference plane due to the via anti-pads being too close together. An example of this can be seen below in the image of a GND plane with too-closely spaced non-grounded vias. This will impede return currents, and can potentially cause EMI problems.
The problem of voids in dense designs can be hard to avoid, especially when you have a large number of signal vias in a particular area. Again, if we were to route a trace over the split in the reference plane caused by voiding, it can be very harmful to EMI performance. The return currents will have to flow around this split in the reference, causing fields to spread, and will increase the radiation and EM signature.
If space allows, a simple fix to mitigate voids in reference planes is to place vias far enough apart from each other so that copper can flow in-between these via anti-pads.
An alternative method is to use HDI vias, either micro-vias to decrease the size of the anti-pads, or blind and buried vias that do not penetrate reference planes. However, this is of course bound to an increase in PCB manufacturing cost.
In any case, make sure to always check your reference planes during the stage of layout and routing for voids. I highly recommend scanning your final Gerber output files for voids as well.
When switching layers with a signal via, we typically also change reference planes (think of a four-layer SIG-GND-GND-SIG board, for example). While we’re still routing on the top layer with a trace, for AC signals (>20 kHz), the return path is directly in the reference plane below. Once we are on the bottom layer, the return path is in the reference plane above.
What happens to the return path and thus the fields when we move along the via in the Z-axis when changing layers? Then fields will spread as they try to find a suitable “attachment point” (a return path), which in turn can be a cause of EMI problems. In such cases, we want to place a transfer via— which is basically a grounded via— close to the signal via. This is to maintain a defined reference and return path while transitioning along the Z. Note that this transfer via only works if the references we are switching between are both of the same type (for example, GND to GND).
If we’re switching from a GND to PWR reference, we need to place a small-valued capacitor stitched between GND and PWR reference close to the transition point.
There are two main reasons for stitching vias. Often in single, multi-layer PCB designs we have multiple ground or power layers, and multiple ground or power copper pours. Without stitching vias (either ground or power vias), the various ground and power layers, as well as any other ground or power copper pours, wouldn't connect well together. A voltage difference would be created between them, in particular at higher frequencies due to impedance, and specifically inductance. To mitigate this, we need to tie these together with vias.
By placing stitching vias, we can tie these layers and pours together at several X-Y locations on the PCB.. Additionally, every time we have copper islands, which can often be not attached at all (or poorly attached) with just a small number of vias, these copper islands can act as antennae, resonate, and then even radiate. This can of course be very harmful to a board’s EMI performance.
The second reason or use for stitching vias is for shielding purposes. In effect, we can use a “wall” of shielding vias to suppress energy of electromagnetic waves (up to a certain frequency) from entering or leaving a section of the PCB. The spacing of shieldings is determined by the maximum frequency apparent in a PCB. For example, for an audio PCB this frequency might be 20 kHz, and for an RF PCB it could be 2.4GHz, if not even higher.
Once you know your maximum frequency of your PCB, we simply need to use this formula to calculate the spacing, where c is the speed of light, ε is the dielectric constant, and f our maximum frequency of interest:
For example, at 2.4 GHz, and with routing on outer-layer (microstrip) traces, the formula gives us a stitching via spacing of 3.4 mm.
In this series of articles, we have examined the basics of vias in PCB design, looking at via parameters, such as drill and pad sizes, types of vias, and what vias can be used for, including transfer and stitching vias.
Make sure to check out all of Altium Designer’s built-in via features, including capabilities for handling more complicated types of vias found on HDI boards, such as micro-vias, blind, and buried.