Why Power Rails Need to be Low Impedance

Kella Knack
|  February 3, 2021
Why Power Rails Need to be Low Impedance

As has been noted in several of my articles as well as in the PCB design information that is available to the industry at large, getting the impedance right is critical for ensuring that a product will operate properly and as designed.

What is not so easily understood and can remain a challenge if not appropriately addressed during the product development phase, is the need to have all power rails be of low impedance so that excessive ripple on signals can be avoided. This article will address this need, including what constitutes a power rail, how it functions, and how fear can be a driving factor in making bad design decisions.

Overview

Impedance is a significant property of transmission lines. It is the resistance that a transmission line presents to the flow of energy along with it. It is composed of three parasitic elements—resistance, capacitance and inductance. As has been demonstrated, at DC or low frequencies, parasitic resistance is the primary determining factor in transmission line impedance. As the frequency gets higher than a few kilohertz, the reactance of the parasitic inductance tends to block or impede the flow of energy. At the same time, the parasitic capacitance tends to shunt the energy to “ground” or the plane. It is these two elements that work together in such a way that the electromagnetic field sees a specific impedance at all frequencies.

The Definition of a Power Rail

A power rail is all or part of a plane layer that is used for some voltage. In virtually all printed circuit boards, some signals, often half of them, have to be routed over the power layers. As a result, it’s unavoidable that whatever ripple or noise that is on a given power plane will be coupled to any signal that is being routed over that particular plane.

Ripple consists of the voltage variations that appear on the Vcc or Vdd rails of power supplies. These variations can be created by the power supply itself or by the varying load currents that cause the supply voltage to drop. In terms of noise, ten possible sources can be generated by design. They include:

In terms of this discussion where nearly all logic devices are CMOS, the most likely sources of noise are reflections, crosstalk, Vdd and ground bounce and ripple on Vdd.

To avoid having excessive ripple on signals, the power rails must be engineered to have very low impedance. As a result, when looking at the delta I versus the ripple, as happens when using the EDA tools that will calculate what the impedance will turn out to be, it’s possible to get an answer that says the impedance is going to be relatively high. The ripple level will still be satisfactory. This happens when the delta I is a really small number. The impedance turns out to be really high, but that’s because there isn’t much of a load. Note: It should be noted that some power rails are low power, but that is not a point of discussion for this article.

The Challenges

The challenge with designing a power rail to be low impedance is that the power rail is most likely to be a portion of a plane and not the entire plane itself. Therefore, it’s necessary to partition the power plane, but when doing so, there will be gaps. As a result, the signals that cross over the gaps will appear to have their return current path disrupted by the gaps. This issue is resolved by engineering that portion of the plane to be very low impedance between the plane and the ground layer underneath it so that the return current finds its way across the gap through that section that is of very low impedance.

The preceding approach eliminates the need to address routing traces over the gaps in the planes that lots of design rules say can’t be done. Figure 1 shows the measured data of signals crossing over a gap that has been engineered in this manner. The blue trace is the signal crossing a gap in the plane over which it is routed. The tiny upward reflection in the center of the trace is where the gap is located. As can be seen, the signal over the gap is not disrupted. (The red trace is a signal on a shorter trace that does not run over a gap).
 

signal crossing
Figure 1. Signal Crossing a 10-mil (.254 mm) Gap in a Power Plane

Underlying all this is the unbending rule that you don’t cut ground planes as they are the structures that tie everything together. Our experience has been that when product developers make cuts in their ground planes, they are either trying to solve a problem they have imagined or they are trying to solve the issue of isolating one circuit from another. The classic, faulty reasoning behind this is to separate the analog and digital grounds. This happens when design engineers misunderstand why there are two different pins on a part, one analog and one digital, that provide the path into the chip. These engineers are often operating from a basis of fear that there will be unwanted interference from one side of the board to the other. As a result, they cut the board to isolate what is, in the final analysis, an imaginary problem.

The previous situation can arise from a product developer who has seen, during simulation, that there is a difference or unwanted interference between one side of a PCB and the other and that it is significant enough that it is going to cause a problem. Whenever we are presented with this type of scenario, we ask to see the measured data from real working hardware. It is only through this kind of evidence that a problem can be readily ascertained.

Summary

In order to avoid excessive ripple of signals, PCB power rails must be of low impedance. Since the power rail is likely most likely to be part of a plane and not the entire plane itself, it is necessary to partition the power plane. This will create gaps, and it will appear that these gaps disrupt the return path of the current. This is resolved by engineering that portion of the plane to be of low impedance so the return current finds its way across these gaps.

Have more questions? Call an expert at Altium.

About Author

About Author

Kella Knack is Vice President of Marketing for Speeding Edge, a company engaged in training, consulting and publishing on high speed design topics such as signal integrity analysis, PCB Design ad EMI control. Previously, she served as a marketing consultant for a broad spectrum of high-tech companies ranging from start-ups to multibillion dollar corporations. She also served as editor for various electronic trade publications covering the PCB, networking and EDA market sectors.

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