Introduction to Printed Circuit Fabrication for the PCB Designer

March 19, 2019 Lee Ritchey

In many companies the PCB designer is expected to know how PCBs are manufactured and how to prepare designs and their documentation in such a way that those PCBs are successfully fabricated, and perform properly at a reasonable price. It is common that the design engineers who work with the PCB designer are not exposed to how PCBs are made, and the materials available from which to make them. These engineers depend on the PCB designer to add that expertise.

The purpose of this article is to introduce PCB designers to how PCBs are manufactured, the materials from which they can be manufactured, and how to make the best set of tradeoffs to arrive at designs that satisfy the requirements of each product.



The name “printed circuit board” is misleading. It implies that the conductors for a PCB are printed onto an insulating substrate much like the way a book is printed. Conductive patterns, usually copper, are formed by bonding a sheet of copper foil to an insulating substrate and etching away the unwanted copper to form the traces and other conductors (subtractive processing), or plating the conductive patterns onto an insulating substrate (additive processing). The subtractive process has been used to manufacture virtually all PCBs currently in use. The additive process has come into use in recent years to manufacture PCBs with very fine features such as those in smartphones, IC package substrates, and smart watches, for example.

The Subtractive Fabrication Process

Since most PCBs are composed of four or more conductive layers, this section will describe that process. Figure 1.1 is the process flow that is followed in the fabrication of a multilayer PB.

Screenshot of Multilayer PCB Fabrication Process

Figure 1.1 Multilayer PCB Fabrication Process

Front End Engineering

Front-end engineering is the step in the fabrication process where the design or CAD files from the customer are used to verify that all clearances and design rules have been followed, and all of the tooling needed to fabricate the PCB are created along with a traveler describing the materials needed, and the process steps involved to create the finished PCB. Among the tooling created are:

  • Artwork to etch all the inner and outer layers
  • Drill tapes used to direct the drills forming all the plated and unplated holes
  • Soldermask artwork
  • Silkscreen artwork
  • Routing guide used to cut the final PCB from its panel
  • Bare board test fixturing

Screenshot of Front-end PCB Engineering Workstation

Figure 1.2 Typical Front-end PCB Engineering Workstation


Inner Layer Processing

Inner layers are formed by exposing the conductor pattern on a piece of laminate that has copper foil bonded to both sides. This results in inner layers being formed in pairs. As a result, multilayer PCBs are always made in even numbers of layers. The first step in this process is to clean the copper foil to make sure there are no blemishes that could result in defects in the conductors in the final layers. Next, a thin film of photosensitive material is bonded to each side of this piece of laminate often called a “detail”. This detail is then placed in an exposure machine that has the artwork pattern for each of the two layers in it, and the pattern is exposed to a light that causes the areas of copper that are to remain on the surface as the detail is rinsed. The copper that will form the conductors on each layer is protected by this pattern as the unwanted copper is etched away.

Figure 1.3 is a typical inner layer exposure machine in the open position showing the artwork for both sides. Once the inner layers have been exposed they are sent to an etching line that performs all of the process steps involved in creating a finished inner layer pair. Figure 1.4 is a typical inner layer processing line. Figure 1.5 shows an inner layer pair emerging from the inner layer etching process.

Once an inner layer pair has been etched, it is sent to an automated optical inspection station (AOI), that compares the pattern etched on each side of the CAD file for each layer to ensure there are no unwanted shorts or opens. Figure 1.6 is a typical AOI station.

Screenshot of Inner Layer Exposure Station

Figure 1.3 Typical Inner Layer Exposure Station

Screenshot of Inner Layer Processing Line

Figure 1.4 Typical Inner Layer Processing Line

Screenshot of Inner Layer Emerging from Processing Line

Figure 1.5 Typical Inner Layer Emerging from Processing Line

Screenshot of AOI Station

Figure 1.6 Typical AOI Station

When an inner layer pair successfully passes AOI it is still not ready to be laminated with other inner layers to form a finished PCB. The copper surfaces are not rough enough to adhere to the resins in the adjacent laminate layers during lamination. A process known as black or brown oxide is used to create the proper degree of roughness to ensure good adhesion during lamination. Figure 1.7 is an inner layer pair after it has been treated with black oxide.

Notice that there are six PCBs formed on a single panel. This is common when a PCB is smaller than the typical panel size processed on a production line. Scroll down to see some typical panel sizes will be listed. Also, notice that there are a variety of features surrounding the PCBs. These features are tooling that the fabricator has created to permit aligning all the layers to each other and to permit accurate alignment of each panel in the various machines involved in drilling, etching and plating.

Inner Layer Pair after Black Oxide Treatment

Figure 1.7 An Inner Layer Pair After Black Oxide Treatment


Once all the inner layers have been created, the next step is to combine them with the other components of the PCB and laminate them together. Figure 1.8 shows the components of a six-layer PCB. They are: two pairs of inner layer laminates, three layers of prepreg (uncured glass resin composite) and sheets of foil for the two outer layers.

Six Layer PCB Stackup entering lamination

Figure 1.8 Typical Six Layer PCB Stackup as it Enters Lamination

Notice that the top and bottom layers are solid copper foil. There have been no patterns etched on them at this point. This is because there must be a solid copper surface on the outside of the PCB to provide a current path for plating copper into the holes and on the traces. The outer layers will only be etched after plating has been completed.

Figure 1.9 shows the station in the fabrication process called layup. It shows a thick metal plate with accurately placed alignment pins onto which the various layers will be stacked prior to lamination. After all the layers have been stacked onto the bottom plate a second plate will be placed over the entire stack and this bundle will be placed in a lamination press such as that shown in Figure 1.10.

Screenshot of Layup Station

Figure 1.9 A Typical Layup Station

The resin in the prepreg layers of the stackup are only partially cured prior to lamination. Once the press has been closed the pressure is applied to the stack and a vacuum has been drawn to remove any trapped air, heat is applied causing the resin in the prepreg layers to melt and flow into the voids in the adjacent etched layers. Once the voids are completely filled with resin the temperature is elevated causing the prepreg resin to solidify. At this point the resin in the laminate layers and the prepreg layers is identical and the stackup is ready for all of the outer layer process steps.

Screenshot of Lamination press loaded with PCB Stacks

Figure 1.10 A Typical Lamination Press Loaded with PCB Stacks

Drilling and Plating

After lamination, panels proceed to a drill station, such as that shown in Figure 1.11, to drill all the through holes that will be plated with copper.

Screenshot of Through hole drill station

Figure 1.11 Typical Through Hole Drill Station


Outer Layer Processing

After lamination and drilling there are a number of process steps a stackup must go through to arrive at a finished PCB. Among these are: plating copper in the holes and on pads and traces; etching away the unwanted copper; applying a surface finish to the exposed copper to preserve its solderability; drilling the unplated holes; applying solder mask and applying silk screened legends. These process steps are shown in Figure 1.12.

Screenshot of Electrolytic outer layer process

Figure 1.12 A Typical Electrolytic Outer Layer Process

The primary reason for plating is to deposit copper in the holes to form vias and other connections to inner layers. The problem with attempting to plate copper in the holes is that they are mainly resin. They cannot be directly plated on and there are burrs and resin smeared onto the inner layer copper to which connections are to be made. Step 2 above removes the drilling burrs and the smeared resin. Steps 3 and 4 deposit a thin layer of tin ions that will adhere to the resin. It should be noted that this tin is not useful for electroplating which is the method used to deposit the final copper layers. In step 4 the panel is submerged in a solution that contains copper sulphate. The copper ions replace the tin ions resulting in a thin layer of copper. This is known as electroless copper because it was deposited without the use of an electric current. Electroless copper is not strong enough to serve as the final copper. Electroplated copper provides the copper strength needed for soldering.

At this point the panel is ready for electroplating copper in the holes and on the traces. In the early days of PCB fabrication, the entire panel was placed in a plating tank and copper was plated over the entire surface and in the holes. This then required etching away the unwanted plated-up copper and the original foil layer everywhere it was not needed. Because of the longer time in the etching solution, producing accurate trace widths was difficult as was forming narrow spaces.

This etching problem was solved by applying a plating resist like that shown in Step 7 exposing only those areas on the surface where plated copper is wanted. Step 8 shows the panel after the copper plating step. Step 9 shows the panel after a metal other than copper has been plated on all the exposed areas that are to remain after the unwanted copper has been etched away (Step 11). Before the lead-free movement began, the protective metal layer was solder. Since the advent of the lead-free movement, this protective layer is usually pure tin. When solder was the protective layer it would melt when wave soldering was done and soldermask on the traces would flake away resulting in solder shorts between traces.

The solder short problem was solved by removing the solder and then applying the solder mask over the bare copper (SMOBC). As with most things, this SMOBC left the pads where component leads are to be soldered exposed. Exposed copper corrodes rapidly resulting in PCBs that don’t solder well.


Surface Finishes

In order to preserve the solderability of component mounting pads some form of corrosion protection is needed. There are several choices. These include:

Hot Air Solder Leveling (HASL)

This finish is applied by dipping the finished PCB into a vat of molten solder and slowly drawing it out between air knives that blow away the excess solder. Figure 1.13 is an example of a PCB with HASL applied to it. The problem with HASL is that the height of solder across QFP pads is uneven, resulting in solder shorts during assembly. The remaining surface finishes are attempts to preserve solderability while preserving the flatness of the soldering surfaces.

Screenshot of PCB with HASL finish

Figure 1.13 A PCB with HASL Finish

Electroplated Gold over Electroplated Nickel

The most reliable PCB surface finish is electroplated gold over electroplated nickel. It is applied in Step 9 in Figure 1.12 and serves as the etch resist. Unfortunately, it is also the most expensive and is used primarily in applications where reliability is more important than cost. Figure 1.14 is an example of such a PCB. Notice that gold is always accompanied by nickel. Gold is the corrosion protection layer. However, if it is plated directly on copper, over time the two metals will alloy at room temperature with copper back on the surface compromising solderability. Nickel is a barrier layer preventing this migration.

Screenshot of Electroplated gold over electroplated nickel

Figure 1.14 Electroplated Gold over Electroplated Nickel

Organic Solder Protection (OSP)

Several conformal coatings have been devised to protect the copper. These are called Organic Solder Protection or OSP. These coatings are designed to protect the exposed copper until soldering and function as a flux during the soldering process. Figure 1.15 is an example of a PCB with OSP. This is the least expensive method of corrosion protection. The problem is that OSP is compromised when it is touched by human fingers. Thus, it is a poor choice for prototyping when it is necessary to handle the PCBs during checkout.

Screenshot of PCB with Entec 106 OSP

Figure 1.15 A PCB with Entec 106 OSP

In an attempt to solve the handling problem with OSP coatings, several metal coatings have been devised that are applied after the PCB outer layers have been etched preventing electroplating. All these finishes are temporary and will degrade with time. None of them have long shelf lives. These coatings are called electroless and they include:

Electroless Nickel/Immersion Gold (ENIG)

This finish is applied with a series of complex chemical baths, some of which include phosphorus molecules that will embed in the nickel. This is one of the most popular surface finishes and is only slightly more expensive than OSP. However, a problem known as “Black Pad” can occur and it results in very weak solder connections that fracture and create open circuits that cannot be repaired, resulting in scrapped assemblies.  A modification of this surface treatment is Electroless Nickel, Electroless palladium. Immersion Gold (ENEPIG). This finish plates a very thin film of palladium between the nickel and the gold. Tests show that this finish still has migration problems.

PCB with ENIG Surface finish

Figure 1.16 A PCB with ENIG Surface Finish

Immersion Silver

Immersion silver has become a common finish for consumer electronics. Its cost is similar to that of OSP. The only downside is the potential for exposed areas of silver to tarnish as much as any silver product will. There is no functional problem related to this tarnishing.

Screenshot of Immersion silver finished PCB

Figure 1.17 Typical Immersion Silver Finished PCB

Immersion Tin

Tin has long been a component of solder used to assemble PCBs. The problem with tin is that it will develop thin tin whiskers between adjacent conductors resulting in short circuits. If immersion silver is used as a protective coating, the assembly operation must make sure that all the tin coated surfaces are covered with solder to avoid the formation of tin whiskers. Figure 1.18 is a typical immersion tin coated PCB.

Screenshot of Immersion tin coated PCB

Figure 1.18 Typical Immersion Tin Coated PCB



When a fabricator uses pattern plating, Step 8 in Figure 1.12, plating thickness will vary with the density of features that are being plated. In areas where there are large numbers of vias and pads, such as a high pin -count BGA, the copper plating will be thinner than in areas where the distribution of features is less dense. This can cause serious problems when there is a need to provide precise, uniform plating thicknesses, such as the holes used for press fit connectors. This is because the current used to plate the copper will be denser where there are few features to plate and less dense where the features are dense.

In order to solve this problem, fabricators often add dummy features to areas of the surface of a PCB that are sparsely populated with features to be plated. These dummy features are not connected to any circuits on the outer layers once the outer layers are etched. They are called “thieving” because they make the distribution of plating current more uniform over the surface of the PCB by robbing current from the sparsely distributed features. Figure 1.17 shows a PCB that has had thieving features added to it. Each fabricator has its own thieving pattern shape but all do the same job.

PCB with thieving added to outer layers

Figure 1.17 A Typical PCB with Thieving Added to the Outer Layers



Virtually all fabricators have equipment that can test the finished PCB to verify that every net is complete and that no nets are shorted to each other. This is called bare board test. This testing can be done with a fixture called a “bed of nails” fixture that has a spring-loaded pin for each component pin in the PCB, or by using a “flying probe” tester that does not require the construction of a test fixture. The bed of nails fixture is faster than the flying probe, but requires the manufacture of a complex test fixture.

All bare board test programs are capable of comparing the net list found in the artwork used to fabricate the PCB to the net list in the CAD system. This should be a required step in the front-end engineering and if the two net lists don’t agree, the job must be put on hold until the disagreement is satisfactorily resolved.


Solder Mask

A protective coating is usually applied to the outside layers of the finished PCB for a number of reasons. Among these are: prevent trace-to-trace shorts when the PCB is wave soldered; cover the vias that connect components to inner layers to prevent solder from wicking down the holes; provide “dams” so solder does not wick away from solder joints; and make a substrate for applying the legend or silk screen. Solder mask is available in a wide variety of colors with green being the most common. Often, prototype PCBs have a different color from production PCBs to distinguish them in the lab.



Silkscreen is the name used for the legends and labels applied to the outer layers of a PCB to denote the names of components, the polarity of capacitors and diodes, and the name and part number of the PCB. It is applied using the same technique used to silkscreen a sweatshirt, thus the name. Silkscreen colors are chosen to contrast with the underlying soldermask.


Typical Panel Sizes

When selecting the dimensions of a PCB, it is often possible to choose the panel size. To achieve the lowest PCB cost it is desirable to use as much of the production panel as possible. Table 1.1 lists the most common panel sizes used to manufacture PCBs. The designer should endeavor to use as much of the available area as possible.

Table 1.1 Typical PCB Panel Sizes


Two Ways to Arrange PCB Layers in a Multilayer PCB

Figure 1.8 depicted the way the layers in a six-layer PCB are arranged when fabricated using the “foil lamination” process. There is a second method for arranging those same layers. It is called “cap lamination” and is shown in Figure 1.18. Notice that with cap lamination the outer layers are part of a piece of laminate in contrast to a piece of copper foil when foil lamination is used. This was the original method used to fabricate all multilayer PCBs. This method is more expensive than foil lamination due to the need to process three pieces of laminate as opposed to only two for foil lamination.

Cap lamination is only used when some special material, such as Rogers 4350, is required between layers 1 and 2.

Screenshot of cap lamination

Figure 1.18 Cap Lamination


Making Two Layer PCBs

Two-layer PCBs are made from a piece of laminate with copper bonded to each side. This piece of laminate enters the process at Step 1 of Figure 1.12 and goes through the same processing as a multilayer PCB.

About the Author

Lee Ritchey

Lee Ritchey is considered to be one of the industry’s premier authorities on high-speed PCB and system design. He is the founder and president of Speeding Edge, an engineering consulting and training company. He conducts on-site private training courses for high technology companies and also teaches courses through Speeding Edge and its partner companies.

In addition, Lee provides consulting services to top manufacturers of many different types of technology products including Internet, server, video display and camera tracking/scanning products. He is currently involved in characterizing materials for ultra high speed data links used throughout the Internet.

Prior to founding Speeding Edge, Ritchey held a number of hardware engineering management positions including Program Manager for 3Com Corporation in Santa Clara and Engineering Manager for Maxtor. Previously, he was co-founder and vice president of engineering and marketing for Shared Resources, a design services company specializing in the design of high-end supercomputer, workstation and imaging products. Earlier in his career, he designed RF and microwave components for the NASA Apollo space program and other space platforms.

Ritchey holds a B.S.E.E. degree from California State University, Sacramento where he graduated as outstanding senior. In 2004, Ritchey contributed a column, “PCB Perspectives” which appeared on a monthly basis in the industry-renowned trade publication, EE Times.

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