ADC/DAC Components With a JESD204 Interface

Created: December 1, 2022
Updated: October 10, 2024

Many simpler systems will include some mixed-signal capability, which is sometimes built into the host controller through an ADC. For more accurate or faster sampling, an external ADC will often be used, including in systems requiring very fast sampling or synthesis with GSps operating rates. What happens when these capabilities need to be implemented across multiple data converters, all of which might be operating at very fast sample rates and synchronized with a reference oscillator?

For advanced mixed-signal systems with multiple data converters, we can’t rely on simpler source-synchronous buses or generic serial interfaces. Thankfully, JEDEC developed a specialty interface just for this type of situation: the JESD204 interface. This interface is intended to ease routing difficulties associated with the use of LVDS lanes when enforcing synchronization across multiple data converters without limiting sample rates to low values.

This article will outline the important design requirements present in the JESD204 interface for use with multiple ADCs and/or DACs operating at fast sample rates. The key that ties this type of system together is the host controller, which is an FPGA with the interface instantiated from vendor IP.

About the JESD204 Interface

ADCs and DACs can operate at very high sampling rates if needed, easily reaching into the GSps range (giga-samples per second). This is a very high sample rate that is appropriate for acquiring RF signals (with an ADC) or generating waveforms at RF repetition rates (with a DAC). When a system is operating with a single data converter, a fast serial interface can be used to send/receive data to/from a system host controller. However, when multiple data converters are present in a system, synchronization is often needed, and this is difficult to enforce a serial interface like LVDS.

This is where the JESD204 interface comes into play. This standardized interface, published by JEDEC, was developed to replace the use of LVDS links between data converters, as well as between each data converter and a system host. The newest revision of the standard (Rev C, or JESD204C) defines a serial protocol that can be used to synchronize multiple ADCs and/or DACs operating at a high sample rate. Primary functions that can be synchronized are signal sampling, synthesis, and timing across multiple data converters.

Because the JESD204 interface was developed as a replacement for LVDS with ADCs/DACs, it is worth comparing the implementation of these two interfaces across multiple data converters:

ADC/DAC components that support the JESD204 interface will have the I/O block built directly into the die, while the system host controller will have the interface instantiated in FPGA interconnect fabric. To ensure system synchronization, ADCs/DACs with a JESD204 interface will include dedicated SYNC/SYSREF pins to support clock triggering from a JESD204C or JESD204B device, respectively.

Advantages of JESD204

It might not be obvious from the above table, but the main advantage of the JESD204 interface for multiple data converters is its timing method. The topology of a JESD204-compliant system involves synchronous sampling across all devices through its reference oscillator distribution, as outlined in the block diagram below. This matches all data converters to the same clock as the host controller, and thus sampling/synthesis is timed to the same clock as the system host.

Sampling/synthesis is triggered in individual data converters with a SYNC pin, which then drives data to stream from individual data converters and into the host controller. The data streams have their own embedded clocks, so the interface can automatically deskew the two data streams. This is the reason the differential data lines from each data converter do not require length matching with a JESD204 interface. Technically, the same kind of deskew feature could be added to a set of cascaded ADCs/DACs that use LVDS, but this would require calculating the deskew in software or in logic.

If you look at the clock/sync distribution between the clock source, host controller, and data converters, there will be some allowed skew budget for the given JESD204 interface instantiated in the main processor. This skew mismatch budget between the longest and shortest traces in the interface must be within some maximum skew value that can be compensated by the interface’s timing scheme. If operating within the skew budget, the interface will be able to detect the mismatches between the resulting incoming data streams on the DATA channels, and the deskew can be compensated in logic. This yields the true phase difference between the sampled signals.

Multiple JESD204 ADCs/DACs vs. Multichannel Components

If you’re familiar with ADCs/DACs, then you should be aware that these components often have multiple input/output channels for signal acquisition/generation. Given that this is the case, it is fair to ask the question: what is the advantage of using separate ADCs with an interface like JESD204 compared to using a single multichannel ADC/DAC?

Some of the challenges present in using a multichannel ADC vs. individual ADC include:

Channel-to-channel crosstalk
Gain, offset, and dynamic range matching
Interleaved sampling
Power dissipation and heat

The same challenges may be present in a multichannel DAC. These components can offer dozens of channels in a single chip, so they do enable very high densities when required. However, there are some conditions that come with that design freedom. Note that there are multichannel ADCs that include a JESD204 interface. The advantages of each approach are outlined below.

Essentially, a multichannel ADC with a single controllable reference may not offer the flexibility to acquire or generate different types of signals in terms of offset, noise level (resolution, dynamic range, and/or gain. With separate ADCs, the sampling/synthesis characteristics can be set independently, although this does increase the component count for each interface. Therefore, the main trade-off is lower density. However, this lower density is required to reduce crosstalk.

The important consideration comes from crosstalk as a function of frequency. At RF frequencies, crosstalk between channels will be more intense than at lower frequencies, and such crosstalk will be reflected across channels in an ADC that would use simultaneous sampling. The solution would be to use interleaved sampling, but now you totally lose the ability to detect phase offsets between channels precisely because they are not being sampled simultaneously. This should also illustrate the advantage of a JESD204-compatible interface for multiple data converters: precise phase determination at RF frequencies.

Example JESD204-Compatible Components

Many components on the market are available that offer fast sampling rates with either a JESD204B or JESD204C interface. Newer components with a JESD204C interface are still hitting the market, and some examples of these will be presented below.

Analog Devices AD9207BBPZ-6G

The AD9207BBPZ-6G from Analog Devices is a dual 12-bit ADC with a maximum sampling rate reaching 6 GSps. The data streaming interface in this component is selectable between JESD204B or JESD204C, with the maximum data streaming rate reaching the interface standard compliant maxima of 15.5 Gbps (JESD204B) or 24.75 Gbps (JESD204C) aggregated across 8 lanes. To control input common-mode noise, this dual-component uses a 1.475 Vpp differential input interface with a high-frequency sampling clock generated with an on-chip PLL. The sampling resolution is also selectable across 8, 12, 16, and 24 bits depending on the JESD204B or the JESD204C mode. A newer version of this component, the AD9213BBPZ-6G, provides many of the same capabilities but with up to 10.25 GSps sampling rate.

Texas Instruments ADC12QJ1600AAVQ1

The ADC12QJ1600AAVQ1 from Texas Instruments is a fast ADC with a maximum sample rate reaching 1.6 GSps with non-interleaved architecture. The component is a quad-channel ADC with JESD204C interface supporting 2 to 8 (quad/dual channel) or 1 to 4 (single channel) serdes lanes at 17.16 Gbps maximum data rate (64B/66B or 8B/10B encoding). The full-power -3 dB input bandwidth is 6 GHz, which provides a flat frequency response FMCW lidar or other pulse-reception-based systems. This input bandwidth is also suitable for direct RF sampling in the L and S bands.

Texas Instruments DAC38RF86IAAVR

The DAC38RF86IAAVR from Texas Instruments is a JESD204 compatible DAC with 14-bit resolution and a maximum sampling rate of 9 GSps. The component offers a direct synthesis of baseband signals or broadcast signals for use in applications like radar or wireless communications. The device provides single-ended output with an integrated balun. Internal clocking is achieved with an integrated NCO, allowing the use of a lower-frequency reference oscillator. To aid the implementation of a JESD204 interface for these components, Texas Instruments provides IP for use in FPGA development.

Other Components Supporting Data Converters

Systems that use data converters operating at very high frequencies are highly specialized and they may require many other components in a signal chain to ensure accurate signal acquisition. These components include digital interfaces with analog interfaces, so the practices used in PCB layout require isolation between these board sections, and this sometimes motivates the use of filters or excess series termination on some nets.

Some of the other components designers might need to support cascaded signal acquisition/synthesis include:

Designers that want to find unique components like JESD204-capable ADCs and DACs can find all their mixed-signal components with the advanced search and filtration features in Octopart. Only Octopart provides advanced search and filtration features to help buyers find components and up-to-date distributor pricing data, parts inventory, and parts specifications. Take a look at our integrated circuits page to find the components you need.

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