Every so often, I get a question from a reader that piques my interest and ends up sparking a lively debate, research dive, or Q&A session. One recent question I received concerns PCB trace length, signaling standards, and component specifications. Here’s the paraphrased question:

This is always a fun question because it can be addressed from multiple angles. In this case, the component was operating over PCIe at high speeds on a standard laminate (Dk ~4 and Df ~0.02 at the high-end of the bandwidth). It shouldn’t be too hard to see that the question is hinting at increasing the trace length from the edge connector to the receiver, and whether or not the component can tolerate the increased distance and still recover a signal in the channel.

How would you go about investigating the maximum PCB trace length you can tolerate in this channel? The reality is that there is no single maximum PCB trace length value for any signaling standard for multiple reasons. Instead we have to look at losses in the channel as the signal propagates. In this particular component, the answer was rather surprising. Keep reading to learn more.

The maximum PCB trace length you can place between two components depends on multiple factors. These include:

**Signaling protocol:**Signaling standards specify a minimum level of performance to which an interconnect should be designed. These requirements don’t guarantee the design will work, but they do give you a baseline to use for design goals.**Component specifications:**Some components can beat the requirements in your signaling standard, but this still doesn’t guarantee the channel will work.**PCB laminate and losses:**All losses in the PCB laminate will reduce the signal amplitude and produce distortion, so these loss sources need to be included when determining trace length.**Skew and phase distortion:**Skew can accumulate in some cases, depending on the routing path, due to the fiber weave effect. This is mostly problematic in the portion of the signal occupying ~20 GHz and higher frequencies, which produces phase distortion in the signal.

With all this in mind, let’s look at where losses accumulate along the channel. The image below shows the total losses in our example channel under consideration. Some of these losses have been lumped together along the length of traces. Regardless of where the losses originate, we simply add them all up in dB, and we can convert this back to a decimal attenuation value if we like.

The point here is this: I don’t really care where the losses come from, they will all add together to limit the power that reaches the receiver. Because the signal can only take so much loss before it becomes unrecoverable, the total loss will limit the PCB trace length to some maximum value.

The insertion loss (specified in dB) along an individual trace is length-dependent and is related to the length and the real part of the propagation constant:

As long as you know the propagation constant and the length of the interconnect, you know the total loss; it’s just the insertion loss plus the return loss at each interface along the interconnect. If you want, you can flip this relation for insertion loss and determine an acceptable loss and maximum trace length as long (as you can determine the propagation constant).

Let’s get back to the original question for a moment. In this exchange, the receiver component specified a maximum PCB trace length in terms of time, rather than in terms of a loss budget or literal trace length. In other words, they are assuming you know the group/phase velocity (or propagation delay) for signals traveling on the interconnect. If you know about dispersion, then you know that you’ll have to do PCB trace length matching vs. frequency because the velocity of the signal varies with frequency.

Whether you see a specific length specified or a time specified, either value will only apply for a specific PCB laminate and trace geometry. If you use a different PCB laminate material or trace geometry, the length value is no longer valid because the losses experienced along that trace length will be different. In this case you need to convert the specified maximum PCB trace length into a new trace length using the propagation constant corresponding to the maximum loss on the interconnect. You can use the ratio:

where γ is the propagation constant for the signal, and L is a length value. Here, I’ve taken the real value of γ as this tells us the loss along the interconnect. If you look at the first equation above, it should be easy to see that the left hand side is just a loss budget. Taking these values together with the appropriate values of your propagation constant gives you the new maximum PCB trace length.

There are a few steps that can be taken at the design level to increase the allowed trace length to prevent excessive loss:

- Use lower loss materials, such as a PTFE-based laminate
- Choose a connector with lower losses
- Remove excess vias and backdrill via stubs
- Try to modify the trace geometry so that it has lower loss

If you’re given a time or length constraint for your interconnect, you just need the propagation constant of your old and new interconnects to determine the new length. If you’re using Altium Designer, you can use the Layer Stack Manager to calculate the propagation delay for your impedance controlled nets, and you can use this to set a trace length limit on the relevant net classes.

For more advanced calculations involving S-parameter extraction, Altium Designer® users can use the EDB Exporter extension to import their design into Ansys field solvers. This is a simple way to qualify a design with a powerful field solver application before beginning a prototyping run.

When you’ve finished your design, and you want to release files to your manufacturer, the Altium 365™ platform makes it easy to collaborate and share your projects. We have only scratched the surface of what is possible to do with Altium Designer on Altium 365. You can check the product page for a more in-depth feature description or one of the On-Demand Webinars.