How to Make a Ground Plane for Your PCB Design

Zachariah Peterson
|  Created: August 10, 2018  |  Updated: May 31, 2024
Creating a Ground Plane for Your PCB Design

I continue to be surprised by the number of designers who have yet to understand the importance of a ground plane. Think back to your basic electromagnetics classes, and you'll see why a large ground plane is important in multi-layer planar structures like PCBs. The ground plane acts as a form of shielding, confining electric fields in certain regions of the PCB stack-up, and it is simply convenient for routing and placing ground connections on components.

If you're one of the many designers who understand the importance and often the necessity of a ground plane, your PCB design software makes it very easy to create planes in a layer stack-up. This article will show how it works, as well as how to set this up in Altium Designer.

Creating Ground Plane | PCB Design | Info graphic

 

Two Types of Copper Layers

All commercial PCB design software defines two types of layers in a PCB stack-up: signal layers and plane layers. The distinction actually has nothing to do with how the layers are traditionally used, and in fact, a signal layer can be used to define a ground plane. The distinction arises in manufacturing outputs in terms of how photoplots of signal and plane layers are displayed in CAM software.

  • Signal layers show a positive view, where the color in the image displays the presence of copper.
  • Plane layers show a negative view, where the color in the image displays the absence of copper.

The distinction is clearly seen in Gerber exports from a PCB layout file, as shown below.

Image signal layer and plane layer from Gerbers

Now back to the original question: how do you make a ground plane in your PCB stack-up?

A plane layer in a PCB stack-up is intended to be completely filled with copper, with the only absence being removal around the board edge and vias passing through the plane. The signal layer could also have complete copper fill, which basically makes it a plane layer, but it will look like a regular signal layer with a positive display in a Gerber output. This leads to two ways to define a plane layer:

  • Designate a layer as a plane layer in the PCB stack-up.
  • Draw in copper on a signal layer to create a plane.

Both options allow you to design multiple large rails into the same layer, or to use the entire layer as a single plane. We'll look at all the options below.

How to Assign Signal and Plane Layers

In Altium Designer, you can assign signal or plane layers in the Layer Stack Manager. The first thing to do when creating an internal plane is to add a design layer specifically for the plane. In the picture below, you can see that two layers have been added as internal planes in the Layer Stack Manager, which is found in the “Design” pulldown menu. They have been named “GND” and “PWR” respectively and occupy layers 2 and 3. Note that planes can also be used on outer layers, such as the stackup I discuss in this article.

Screenshot of Altium Designer layer stack manager in creating a ground plane

Creating Internal Plane layers using Altium Designer’s Layer Stack Manager

Once you have set everything up, you are ready to assign a net name to the plane layer. Open the PCB Editor, and navigate to the internal plane layer. Double-click the colored region and a net assignment dialog will appear. Select the relevant net from the dropdown menu, and you are finished. Any vias or through-hole pins that also connect to this net will automatically connect to the internal plane.

An example of via connections to a net can be found in the left panel of the picture below. Note that the pins and vias do not have any visible connections yet to the plane. This is because the net name has not been assigned. You can also see on the left side of the connection menu that pops up when you double-click on that layer within the layout session. This same menu is used to name both single and split planes.

In the drop-down menu on the left side of the picture above we have selected “GND” as the net name that we want for this internal plane. This way it will match the GND net of the pins that you can see in the picture.

 

Once a net name has been selected, vias and through-holes are directly connected to the plane. If the relief connect rule is enabled in the PcbDoc, the pins will have thermal pad connections applied automatically as shown in the right side of the picture. Remember that this is a negative plane, so the metal of the thermal spokes and the plane area are represented by the darker color.

Creating a Plane With Polygon Pour

If you designate a signal layer in the PCB stack-up, then you can turn it into a plane by drawing in a copper pour with the drawing tools in your PCB design software. Draw out the plane manually in the copper layer with the drawing tools and assign that region of copper to the appropriate net.

Now we’ll create a positive plane or a “Polygon Pour”. On the left side of the picture below you can see that this signal layer does not have any metal on it yet. To create the polygon pour you can either use the pulldown menu command “Place > Polygon Pour”, or you can click on the polygon icon in the active bar at the top of the session window.

While in the polygon pour mode, you will click where you want to place a vertex of the plane that you are creating. If you make a mistake simply use your backspace key to remove the last placed vertex. Once you are finished, right-click in the workspace to exit the polygon pour mode. On the right side of the picture above, you will see the plane that you created assumes the color of the layer that you are working on. You will note though that there aren’t any connections yet to the pins and vias in this plane layer.

Screenshot of Altium Designer polygon pour in creating a ground plane

Creating a Polygon Pour in Altium Designer

Once the polygon is placed in the PCB layout, it needs to be assigned to a net; select the polygon you just created and go to the Properties panel. As you can see in the picture below, you will have a list of nets that can be assigned to the polygon. Again, we have selected the GND net.

Screenshot of Altium Designer net name for polygon pour in creating a ground plane

Assigning the net name to the polygon pour

There are other options and values that you can set up in this panel for your polygon. As you can see above, there are options for copper islands, arcs, and nets as well as setting your plane up as a solid pour or hatched

While the polygon is still selected you will next need to re-pour the plane in order to force the connections between the polygon and any nearby objects assigned to the same net; this is required any time you modify a polygon. To do this, right-click on the selected polygon in the PCB Editor window and select Polygon Actions -> Repour Selected. You can also use the T + G + A hotkey to repour all polygons.

Screenshot of Altium Designer repour polygon pour in creating a ground plane

Re-pouring the polygon pour to connect the net

When repouring a polygon over any vias, SMD pads, or through-hole pads, the design rules engine will enforce a connection style between the polygon and the pad. In the image below you can see that the polygon (shown in red) is now connected directly to the vias and through-hole pad with a thermal relief. Once the polygon is repoured on this layer, the thermal relief spoke connection will be visible.

Screenshot of Altium Designer polygon pour ground plane in creating a ground plane

A completed polygon pour ground plane in Altium Designer

If you determine you do not need an entire layer filled with copper to form a plane, you can split the layer into multiple rails by drawing different polygons. While not recommended for ground, it is very common with power rails. One practice that is common in designs that require digital power rails or high-current DC rails is to use large sections of copper pour and place them on the same layer. This layer, for example, would be your power layer, and all the rails would have to share space on this layer. This is a common approach in 6-layer stack-ups or in less-dense 4-layer stack-ups. Follow the steps above to implement this type of design.

Splitting a Plane Layer Into Rails

An alternative to drawing multiple polygons onto a signal layer is to draw splits in a plane layer to form multiple rails. While you should be careful of the signal integrity and power integrity consequences of doing this, skilled designers who split planes into different rails can achieve a very convenient way to route power into groups of components or circuits. Doing this on a plane layer involves manually drawing out the split regions on the plane layer, then assigning a net name to each rail formed after the split.

In Altium Designer, you can place any configuration of lines, arcs, tracks, and fills in an internal plane to define a split and create multiple rails. The easiest way to draw split plane is to use the Place -> Line command and manually draw out the boundary of the new rail in the plane layer. Once this is drawn, the new rail can be assigned to a net using the same process shown above for a uniform plane. Once this is complete, the split plane regions can be selected individually, such as is shown in the image below.

Polygon and Plane Connect Styles

One item to complete is to assign a desired size for thermal relief pads and clearances that you want on your plane layers, or to remove these reliefs entirely. Altium Designer will have a default setting when you create a new PcbDoc file, but you may want to change this connection style setting for your particular design.

To do this we will open up the design rules in Altium Designer which are also found in the “Design” pulldown menu. As you can see in the picture below, you have the ability to specify the expansion, air gap, and conductor width of a thermal relief pad. The thermal or connection styles can be set using two design rules:

  • Power Plane Connect Style (also applies to ground)
  • Polygon Connect Style

These rules allow you to specify the type of connection you want and where the rules are applied. For example, using the query language in Altium Designer, you can apply the rules to vias, SMD pads, through-hole pins, or all of these. In the example below you can see how the pad connection is set for thermal relief while the via connection is set as a direct (solid) connection to the plane.

Screenshot of Altium Designer plane connect styles in creating a ground plane

Setting up thermal relief pads in the design rules of Altium Designer

Plane and Board Edge Clearances

You may have noticed above that copper clearances must be applied around vias passing through plane layers and polygons. Planes and polygons also must have some clearance to the board edge (called copper pullback), which is typically 10 mils.

Because planes and polygons are different objects in Altium Designer, there are different design rules used to apply clearances between vias/through-hole pads and these objects:

These clearances can be applied to individual nets or net classes using the "Where Object Matches" field or with the query engine.

To apply a clearance to a polygon, open the PCB Rules and Constraints Editor and navigate to the Electrical -> Clearance section. This section is where clearances are applied between all objects that are not components, planes, or the board edge. For example, if polygon-to-via clearance needs to be increased, this can be applied with a hole clearance or a pad clearance (the latter assuming NFPs are maintained in the design).

To apply a universal clearance to a plane, navigate to the Plane -> PlaneClearance section. The option shown in the PCB Rules and Constraints Editor shows a plane clearance value from a hole wall to nearby copper, or from the internal via pad/through-hole pad to nearby copper. Once applied in the PCB Rules and Constraints Editor, the clearance rule will be enforced in the plane automatically and the copper clearance will be visible immediately.

Finally, the board edge clearance for polygons is applied in the Manufacturing -> Board Outline Clearance section of the PCB Rules and Constraints Editor. The value you should use depends on your manufacturer's tolerances in milling boards from a panel, but the value is typically 8 mil or 10 mil. If you have completed the PCB layout before applying this rule, you might see several DRC errors in the layout for any objects near the board edge. Once applied, polygons spanning throughout the PCB will need to be repoured in order to enforce the edge clearance.

Default constraints for the Board Outline Clearance rule

There is much more in Altium Designer for the creation of power planes and ground connection capabilities than what we have shown you here. Altium Designer is both powerful and flexible, making it one of the best PCB design software systems available. It will provide you with the tools that you need to expertly handle the design challenges that you are working with today.

Would you like to find out more about how to make a ground plane on your next PCB design in Altium Designer? Talk to an expert at Altium.

About Author

About Author

Zachariah Peterson has an extensive technical background in academia and industry. He currently provides research, design, and marketing services to companies in the electronics industry. Prior to working in the PCB industry, he taught at Portland State University and conducted research on random laser theory, materials, and stability. His background in scientific research spans topics in nanoparticle lasers, electronic and optoelectronic semiconductor devices, environmental sensors, and stochastics. His work has been published in over a dozen peer-reviewed journals and conference proceedings, and he has written 2500+ technical articles on PCB design for a number of companies. He is a member of IEEE Photonics Society, IEEE Electronics Packaging Society, American Physical Society, and the Printed Circuit Engineering Association (PCEA). He previously served as a voting member on the INCITS Quantum Computing Technical Advisory Committee working on technical standards for quantum electronics, and he currently serves on the IEEE P3186 Working Group focused on Port Interface Representing Photonic Signals Using SPICE-class Circuit Simulators.

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