How to Take a Phase Noise Measurement for High Speed Signals
There are plenty of noise sources in your PCB, and phase noise can be one of those sources that is difficult to pin down in a real board. If you’re debugging a high speed board with high BER, then you’ll likely need to gather a phase noise measurement from the failing board section, or from your clock.
Without getting too deep into the IC side of a system, phase noise may be an inherent property of the component you are using, such as the PLLs inside SerDes components. In other cases, other components in your board, your layout, and even your substrate will create random signal skewing. When the source of this jitter is not obvious, you’ll want to gather a phase noise measurement for the suspect component, both as a solitary DUT and in your suspect board.
What are Phase Noise and Jitter?
Most digital designers use the term “jitter” to refer to timing noise, where there are variations in the time at which a signal is launched on an interconnect. The analog designer is more likely to use the term “phase noise,” meaning the phase difference between an analog signal and its reference noisy and varies randomly. The terms are interrelated and refer to the same thing: variations in signal timing in the time-domain (jitter) or the frequency domain (phase noise).
In the frequency domain, a phase noise measurement might look something like the graph shown below. Here, a signal is sourced with carrier frequency at f0, and there is a weaker frequency being sourced at f1. The presence of phase noise on f0 effectively increases the signal’s bandwidth and raises the noise floor. If the signal at f1 is weak enough, this signal will be hidden behind the phase noise from f0.
Jitter is the manifestation of phase noise as seen in the time domain. Jitter can be seen directly in an eye diagram and is easy to identify. Normally, the RMS jitter is the important parameter used to quantify acceptable BER values. To see an example of jitter in an eye diagram and how it can be quantified in the time domain, take a look at this recent article.
Taking a Successful Phase Noise Measurement
What motivates the need for a phase noise measurement? If you’re working with a digital system and you notice jitter in your eye diagram, you’ll need to identify the strongest sources of phase noise that cause jitter in your device. Diagnosing phase noise on an analog signal can be as simple as comparing the rated bandwidth with the measured bandwidth.
The last point above represents a lower limit on possible phase noise you can expect to see in your system. If phase noise appears to be a problem, check the datasheet for your clock/reference oscillator. If the inherent oscillator noise accounts for the majority of your measured phase noise, then you may just need a more stable oscillator/PLL.
A phase noise measurement can be gathered directly from your board using a spectrum analyzer with a near-field probe. Phase noise can also be measured with a spectrum analyzer connected to a DUT with a test fixture (be sure to de-embed the S-parameters for your connectors). Here, you’re measuring a power spectral density, so the phase noise you measure is a function of the measurement bandwidth. The accepted standard is to gather successive measurements in a 1 Hz bandwidth.
Interpreting Phase Noise Data
When interpreting phase noise measurements, your goal is to identify the most prominent sources of noise and reduce them in succession. Four common sources of phase noise that produce jitter are:
- Excessive transient ringing on the source component’s PDN. It doesn’t hurt to measure this.
- Noise coupling from a switch-mode power supply into a data stream or system clock.
- Thermal noise: phase noise is larger at higher temperatures. Shot noise and 1/f noise are also important.
- Large variations in dielectric constant of your substrate. Solve this by using a substrate with a tighter fiber weave. Roger Coonrod provides some great advice on selecting substrates to reduce phase noise.
- Inherent phase noise on a reference oscillator, or inherent jitter on the system clock. These are normally reduced in ultra-fast systems with a PLL.
The goal here is to identify the most prominent source of phase noise and reduce it first. If this brings your system within specs, then consider your work done. There will always be some amount of phase noise in a system, regardless of the Q value of your clock/reference oscillator. However, if you can get your BER values or other performance requirements within spec, then you’ve done your job successfully.
You can spot the culprit noise sources visually in a phase noise plot and compare them to known noise sources in your board. An example measurement with several phase noise spurs is shown below.
Notice the strong spurs in the graph above, which arise from a variety of sources. The noise above can be compared to the reference specifications for the relevant components in your board. This would be done by drawing a line through the phase noise spec point with -10 dBc/Hz slope; any portion of the noise spectrum that rises above this line would fall outside the allowed phase noise tolerance and would need to be suppressed in the design.
Acceptable phase noise levels can be quantified in terms of an RMS phase jitter value using the following formula. Note that L(f) is the logarithmic phase noise data, thus the odd factors of 10 appear in the integral to convert this back to a linear dataset. The integral here is taken over the relevant signal range.
Once you’ve determined any layout or component changes during debugging, the design tools in Altium Designer® are ideal for modifying your design and finding candidate replacement components. You can access the components you need from the Manufacturer Part Search panel, and you can easily modify your board with best-in-class routing and layout tools. You can also import your designs from other CAD tools and get the job done right with Altium Designer.