Introduction to High Speed PCB Designing: Techniques for Avoiding Crosstalk

Zachariah Peterson
|  Created: November 8, 2017  |  Updated: August 23, 2023
Introduction to High Speed PCB Designing: How to Eliminate Crosstalk

High-speed PCB designs can bring many challenges when certain guidelines are not followed. Some of the most important (and most common) high-speed design guidelines don't just ensure correct routing with low noise, they also help prevent crosstalk.

Crosstalk in PCBs is the unintentional electromagnetic coupling between traces. In other words, crosstalk occurs when a digital pulse on one trace induces a similar signal on the other trace, even though they are not physically touching each other. This can happen when the spacing between parallel traces in PCB is tight and the reference plane is far from the traces, or when there is no reference plane below two traces that are interfering. But with some very basic design techniques, you can solve many crosstalk problems.

What is Crosstalk in High-Speed PCB Design?

Crosstalk always occurs in PCBs, it is just a matter of determining whether that crosstalk is so great that you need to do something to solve the problem. Crosstalk occurs between two parallel traces running next to each other on the same layer. There is an even greater possibility, though, for crosstalk in PCB to occur between two parallel traces running next to each other on adjacent layers; this is called broadside coupling.

Consider two traces in PCB running parallel to each other. When the signal in one trace is switching (the "aggressor"), it will induce a voltage/current into the other trace. This induced signal will then be observed at the driver end (near-end crosstalk) and the receiver end (far-end crosstalk) of the victim interconnect. Even though the traces may be maintaining the minimum spacing for manufacturing purposes, they may not be enough for electromagnetic purposes. In general, when traces are closer together, you could have stronger crosstalk. This can be seen clearly in the example simulation results below.

NEXT FEXT crosstalk
NEXT FEXT crosstalk
Increasing the spacing between traces from 1x trace width to 3x trace width provides a significant decrease in crosstalk.

As I've discussed in this other article on crosstalk, the strength of crosstalk depends on the aggressor signal's edge rate, not on data rate or clock rate.

The other point that introductory designers overlook is crosstalk between differential pairs, appropriately referred to as differential crosstalk. In general, differential pairs can create crosstalk into single-ended signals and into other differential pairs, despite myths that state otherwise. Because crosstalk occurs in linear networks, the phenomenon is reciprocal; single-ended signals can generate crosstalk into differential pairs.

Blue highlighted traces on a black and white circuit board
Trace spacing to eliminate crosstalk is typically larger than regular trace spacing requirements

Suppressing Crosstalk from Your High-Speed Design

While you can never totally eliminate crosstalk, there are simple steps you can take to reduce the intensity of any induced crosstalk so that it is less noticeable and does not create errors at I/Os on the victim line. Here is the main list of high-speed design techniques that will greatly suppress crosstalk:

  1. Route digital signals over a continuous ground plane. In today's PCBs, this is a mandatory requirement anyways, regardless of whether your traces must be designed to a target impedance.

  2. When the distance to ground is larger, your signals need to be spaced out by a larger distance. A conservative rule of thumb is gap = 3W (W = trace width).

  3. When signals over a ground plane create too much crosstalk, bring ground closer to the signals. This might require a 4 layer board at minimum. Bringing ground closer to signals can also allow violation of the 3W rule.

  4. Typically, you may need to increase the spacing between a clock line and a signal line in a source-synchronous bus so that you retain timing margins but minimize crosstalk. The same gap = 3W rule of thumb also works here.

  5. Asynchronous signals or configuration signals (like RESET, INTERRUPT, ENABLE, etc.) may need to be routed away from high-speed buses. They can be routed next to on-and-off or power-up signals though because those signals are rarely used during the normal operation of the circuit board. They could also be filtered to help remove fast crosstalk pulses because they do not have a rise time requirement to toggle a pin, they can change slowly.

  6. If routing signals on different signal layers, place a ground reference between these layers in order to shield the signal layers from each other.

  7. If Rule #6 is not possible (such as in a 6-layer stackup with two internal signal layers). Try to carve out specific board regions for high-speed channels. If the board will fill with signals, use orthogonal routin (horizontal and vertical routing directions on different layers).

Within this list, Rule #1 is most important. It is the simplest and most effective design choice for a modern system that will help reduce crosstalk on a PCB. Following that, Rules #2 and #3 are equally important as they relate to the design of your stackup. This then brings up the question: what 

How Do We Know if There is Too Much Crosstalk?

As I stated above, you will always have some crosstalk in a PCB, but many times you may not notice it is present. However, if there is a significant amount of crosstalk, how will you know if it is too much?

There are some simple ways to quickly determine if crosstalk will be a problem, and there are more complex evaluations that are typically required in standardized interfaces (such as Ethernet, Infiniband, serdes lanes, DDR, etc.). The simple method for determining if there is too much crosstalk is to look in the time domain. There are also signal integrity simulators that enable analysis of your high-speed design for potential crosstalk problems.

In the frequency domain, we would use an S-parameter mask to compare with the crosstalk we observe in a PCB signal integrity simulation. S-parameter masks basically provide an upper or lower limit on a particular signal integrity metric up to some frequency limit. For a standardized digital interface, the important point is to compare against the S-parameter limits defined by the mask, which can be inspected visually in a graph.

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About Author

About Author

Zachariah Peterson has an extensive technical background in academia and industry. He currently provides research, design, and marketing services to companies in the electronics industry. Prior to working in the PCB industry, he taught at Portland State University and conducted research on random laser theory, materials, and stability. His background in scientific research spans topics in nanoparticle lasers, electronic and optoelectronic semiconductor devices, environmental sensors, and stochastics. His work has been published in over a dozen peer-reviewed journals and conference proceedings, and he has written 2500+ technical articles on PCB design for a number of companies. He is a member of IEEE Photonics Society, IEEE Electronics Packaging Society, American Physical Society, and the Printed Circuit Engineering Association (PCEA). He previously served as a voting member on the INCITS Quantum Computing Technical Advisory Committee working on technical standards for quantum electronics, and he currently serves on the IEEE P3186 Working Group focused on Port Interface Representing Photonic Signals Using SPICE-class Circuit Simulators.

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