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    PCIe BGA Fanouts and Escape Routing

    Zachariah Peterson
    |  May 5, 2019

    IC for PCIe BGA fanouts

    One of many BGAs you can use with PCIe

    With all the chips that appear on a PCI or PCIe card, laying out and routing these boards might seem extremely complicated. However, the standardized architecture of PCIe provides considerable flexibility for designers.

    One issue that is a bit complicated is PCIe BGA fanouts for components on these cards. The trick to implementing a fanout and escape routing strategy is ensuring that you comply with the PCIe layout and routing specifications. With this in mind, let’s dig into some tips for fanouts and escape routing.

    PCIe BGA Fanouts

    As is typical with most components with BGAs, there is no golden rule regarding BGA fanouts, and the correct choice depends on the pitch between balls in the BGA. Component manufacturers may recommend different fanout strategies for a particular component, so it is best to check their datasheets before implementing a fanout strategy.

    The actual escape routing strategy will depend in part on the layer stack. PCIe devices are mostly built on 4 layer boards, although 6 layer boards are also a common choice. Regardless of the layer count, the overall thickness of the card is limited to 1.57 mm. With four layer boards, your routing space will be limited to two layers due to the two internal copper planes.

    With very coarse pitch BGAs, you may be able to route directly out of the package without placing vias on your signal lines. The PCIe routing guidelines specify symmetric routing, even under a BGA. As you route beneath the package between neighboring balls, you may need to place a bend in a signal line to make the desired connection. Try to mirror any bends in both traces on a differential pair as closely as possible. It is best to route a differential pair between pads, rather than placing pads between traces in a pair.

    A dog bone fanout strategy is appropriate for coarse to intermediate pitch BGAs, but the trick is to keep traces coupled beneath the package. This can be difficult considering the limits on board thickness, as this limits the available layer count. The requirement to route differential pairs between balls actually makes it easier to reach the first two rows in the BGA directly on the top signal layer (i.e., without vias) compared to a typical dog bone fanout strategy. On the inner rows, you can then use a dog bone fanout with vias to reach another signal layer. Be sure to include the appropriate anti-pad diameter when routing through copper layers.

    In the case of extremely fine pitch BGAs with very high pin count, you may have no choice but to opt for a higher layer count with HDI routing. The fine BGA pitch may not support a typical fanout strategy due to the shear number of required connections. You’ll want to use VIPPO vias to access the inner layers of your board as the plating in VIPPO will prevent solder from wicking to the back side of the board.

    Dog bone fanout for a BGA on a green PCB
    Typical dog bone fanout for a BGA

    Routing After Escape

    Once your traces escape from the BGA, what happens next depends on the device that will be mounted on the BGA. Although the official PCIe layout and routing specifications define allowed maximum trace lengths, differential impedance values, and maximum number of vias that can appear on an interconnect, your components may carry different requirements. Specifications on routing outside the BGA are more a function of the component and signalling standard being used, rather than simply looking at the maximum allowances in PCIe standards.

    These varying minimum, typical, and maximum routing requirements with different components arise due to sensitive tolerances on component themselves. These requirements tend to be more stringent than the allowances provided in the official PCIe standard, regardless of the generation. As such, you should always check the datasheets for your components before you begin designing your layout and routing.

    PCIe card with HDI routing and ICs

    Keeping the impedance differential traces consistent and within the required tolerance takes PCB design software with controlled impedance design and routing features. This allows autorouting or interactive routing features to automatically set trace spacing and geometry as you route. Make sure to obey the “5W” rule on spacing between differential pairs and mirror any deviations in one trace in the neighboring trace in order to ensure symmetricity. Also, be sure you define the tolerances on length mismatch according to your chosen signalling standard.

    Today’s device speeds require designers to define their differential trace geometry with consistent characteristic impedance as design rules that conform to the PCIe standards. Working with rules-driven PCB design software like Altium Designer® greatly simplifies layout and routing, making it much easier to design your board to PCIe specifications. The Active Route package is just one of many tools in Altium Designer that helps you design to these important standards.

    Now you can download a free trial of Altium Designer and learn more about the layout, routing, and verification features. Talk to an Altium expert today to learn more.

    About Author

    About Author

    Zachariah Peterson has an extensive technical background in academia and industry. Prior to working in the PCB industry, he taught at Portland State University. He conducted his Physics M.S. research on chemisorptive gas sensors and his Applied Physics Ph.D. research on random laser theory and stability.His background in scientific research spans topics in nanoparticle lasers, electronic and optoelectronic semiconductor devices, environmental systems, and financial analytics. His work has been published in several peer-reviewed journals and conference proceedings, and he has written hundreds of technical blogs on PCB design for a number of companies. Zachariah works with other companies in the PCB industry providing design and research services. He is a member of IEEE Photonics Society and the American Physical Society.

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