Pin-Package Delay and Via Delay in High Speed Length Tuning
The race is on to keep signals in sync
Take a look at the inside of an integrated circuit package, and you’ll find a number of wires bonded to the semiconductor die and the pads at the edge of the component. In the electronics world, signals need to travel across these bond wires and pads before they hit a PCB trace. As you look around the edge of an IC, these bond wires all have different lengths, and they incur different levels of delay and contribute to signal skew.
Vias can also induce some delay on any interconnect, which is a function of the via’s length, its inductance, and its capacitance. Signal behavior on vias can be quite complicated to describe analytically, particularly when you start looking at higher frequencies and evanescent coupling along the edge of an interconnect. With some simple pieces of information, you can compensate for pin-package delay and via delay in your PCB interconnects.
Pin-Package Delay in Length Tuning
All signals, whether electrical or optical, travel at a finite speed. This means any section of an interconnect which a signal must traverse will incur some travel time. The bond wires in an integrated circuit, solder balls on a BGA component, pins on a through-hole component, and any other piece of metal that separates a trace and semiconductor die requires some time to traverse, and your designs should account for this delay during length matching.
Pin-package delay is the time required for a signal to traverse the pad and bond wire of a component. IC manufacturers that are worth their brand name will measure this and provide the delay value in the component datasheets; these delays are usually on the order of tens or hundreds of picoseconds. As an example, pin-package delays in some Xilinx FPGAs can vary from 80 to 160 ps.
You’re probably asking: why do we need to worry about this? The simple answer is any trace length mismatch should be included when length tuning high-speed signals in order to prevent skew. The exact skew limits between parallel data will vary depending on your design and signalling standard, and length matching must be used to ensure signals arrive within these limits. Accounting for all skew sources is particularly important in length matching for differential pairs in order to suppress common-mode noise.
Variations in the lengths of these bond wires and parasitics leads to variations in pin-package delay.
With relatively slower signals (>1 ns rise time) and slower data rates (<500 MHz), you might not need to worry about the pin-package delay in an interconnect, especially if you have a large noise margin at the receiver and are working at a higher voltage (3.3. V or 5 V). 500 MHz is generally taken as the lower limit on data rate beyond which pin-package delay should be included. Beyond this data rate, the signal repetition rate will be less than 2 ns, and the signal rise time will be even faster. This creates a situation where the pin-package delay is comparable to the data repetition rate and the rise time, and signals could completely desynchronize simply by travelling over bond wires and component pads.
Accounting for Via Delay
Just as is the case with pins and bond wires in an integrated circuit, the signal speed in a via can differ from the signal speed along the traces connected to it, especially when you look along the length of the via. To ensure the signal speed is known with high precision, vias should be carefully characterized experimentally (read this article in Signal Integrity Journal), or characterized theoretically through simulations.
The signal speed across a via depends on a number of factors, including the pad-antipad distance, the fiber weave effect through the board cross section, and plating imperfections along the length of the via (especially in high aspect ratio vias). Vias that make a layer transition while changing reference planes will also see a sudden impedance and propagation delay change across the length of the via. If we consider a through-hole via in a 1.57 mm FR4 board, the one-way via delay is about 10 ps (if we assume uniform dielectric constant across the length of the via). In a real via, the delay will be much different, depending on which layers are traversed and on the presence of nearby conductors (i.e., due to parasitic inductance and capacitance).
EM field simulations for these vias can help you determine skew during length matching
Accounting for via delay and via impedance is easiest when your routing tools include a 3D electromagnetic field solver. While you can calculate variations in via propagation delay by hand (in principle), you will be unable to account for any fiber weave effects unless you take a probabilistic approach. Clearly, this is an intractable exercise that demands the right design tools.
By default, most PCB design programs with length matching capabilities will set the pin-package delay to zero length or zero time. If you obtain component models from your manufacturer, the IBIS 6 documentation for the particular component should include the pin-package delay. This will be specified as either a length or time. When you include these delays for each component pin in your schematic, you now have the information you need for ultra-accurate length tuning or delay tuning as you route your signal traces.
The new-and-improved routing tools in Altium Designer® allow you to specify the pin-package delay for a component directly from the schematic. You’ll also be able to account for via delay during length tuning using a cutting-edge field solver from Simbeor. This solver is built into the routing features and is used to simulate the propagation delay on a trace, which is then used for length matching across multiple signal nets. You’ll also have a complete set of tools for building schematics, managing components, and preparing deliverables for your manufacturer.