A Power Integrity Primer
Table of Contents
Almost anywhere you look these days, be it academic textbooks, presentations at technical conferences, websites for various products linked to printed circuit board (PCB) design or technical articles posted on your favorite engineering design and automation (EDA) website, the primary challenge in designing today’s high-speed systems is firmly tied to the design of the power delivery system (PDS). It is the “make or break” functionality for a newly designed product or even a new iteration of one that has been around for a few years. A thorough understanding of power integrity is crucial to the success of designing a functional PDS.
This power integrity tutorial will describe the fundamentals of power integrity (PI), the elements that comprise it, the challenges encountered in achieving it and what the future holds relative to it. The key takeaway: if you do a good job designing your PDS, you have taken care of the PI needs for your PCB. In addition, you'll reduce some signal integrity problems to the point where they may not be noticeable in your PCB.
In the most succinct terms, power integrity means delivering the power to integrated circuits (ICs) on a PCB with enough quality that the circuit is always reliable. Beyond supplying adequate power to the active components, power integrity also encompasses maintaining power at a constant level and minimizing signal losses.
It’s a given that power integrity is inherent in understanding power delivery and the integrated design of high-speed systems; we include a power integrity tutorial as part of our regular two-day courses that we teach under the auspices of Speeding Edge. But, because it is so integral, significant and, these days, increasingly complex, we have developed a one-day stand-alone power integrity tutorial just to address how to design a working PDS.
Lee Ritchey, Founder and President of Speeding Edge and the only instructor we use for our PDS classes notes, “PI and PDS design are so important in today’s designs that we find the only good way for it to be understood is to have a separate day that focuses on it. That’s because power integrity spreads across the entire system—the board, the chip, the chip package and the system itself.”
Fundamentally, the issues addressed include:
• Keeping voltage ripple within acceptable limits.
• Controlling ground bounce and other switching noises such as SSN.
• Controlling electromagnetic interference (EMI) and electromagnetic compatibility (EMC).
• At high currents, maintaining the proper DC voltage level.
The image below shows a voltage measurement from a PDS supplying current to an IC, which is switching with fast edge rate. The IC switches periodically, which produces the periodic ripples superimposed on a nearly constant DC level. These ripples are excessively large and can interfere with the ICs connected to the PDS. One of the major goals in any power integrity tutorial is to smooth out these ripples as much as possible so that they do not create new signal integrity problems.
Ritchey explains, “The first step in establishing and maintaining power integrity is knowing what the loads require. This is the hardest part of the process. This comes down to getting the information on what you need to deliver to the ICs.”
“The reason this is so hard,” Ritchey continues, “is because there is no standard for communicating this information. It should come from the component supplier not in the applications note but in the datasheet. The application’s note is ‘how do I use this part?’ The datasheet is ‘how is this part constructed and what’s needed for it to operate properly?’”
Ritchey adds, “It happens that most applications notes attempt to tell you how to deliver the power, but historically that’s been useless information because it has been so generic. The classic example is the 0.1, 0.01 microfarad info, but those are purely arbitrary kinds of things that don’t really speak to the problem.”
“This stems from the history of app notes and the shortcomings inherent within them. The reality is that IC suppliers would not make apps notes unless they were forced to. And, when they do make the app notes, they typically get people who do not understand the parts to create the notes. This information should come from the engineers who design the part, but in most cases, those people don’t want to be bothered. They offload it to somebody else who does not have the proper background or comprehension to create the applications note.”
Once you have completed the frequently difficult process of determining what the loads are, the next step is figuring out how you are going to provide that power to the ICs. Ritchey states, “This involves converting the power from the AC mains down to the DC voltages that are required by the ICs.” The challenge is that not all electric products operate in this manner. Many of them, especially mobile devices, are only powered by batteries. “The problem is still the same,” Ritchey explains. “There is a primary or ‘raw’ source of power that is converted to the final voltage that an IC requires. Anymore, almost nothing runs directly from batteries. There is always a converter. Even a mobile device such as a cell phone may have a dozen different supply rails. In this instance, you have a single voltage battery or a single 110-volt power supply, and you have to create a whole variety of what are almost always very low voltages.”
The voltage issue is complicated by the extremely high currents that are in concert with these voltages. As Ritchey notes, “Until these high currents showed up we didn’t pay much attention to the DC voltage drops in the planes because the currents were not a big issue. Now, in some cases, it’s the high current that dominates the design. And the question becomes ‘how do I get enough copper to get the current into the IC’?”
The foregoing is not the task of the board designer but the person designing the ICs who has to take all this into account. Ritchey notes, “The IC designer has to get the high current into the part at the right place. I wonder about that sometimes. How do you get 160 amps through all the balls and through the package onto the IC without causing a fire? If you look at those kinds of ICs, sometimes there are 200 of the [connection] balls for power and ground.”
For a long time, the most difficult portions of board designs were signal integrity (SI) issues. When data paths consisted of single-ended signaling, they were subject to two unwanted types of noise: ripple on Vdd and Vdd and ground bounce. As logic speeds increased, these two types of noise became so large that it was not possible to build packages that had inductances which were low enough and power subsystems with sufficient high-quality capacitance to contain the noise. This led to the use of differential signaling. It has become the predominant method for creating data paths, and there are great, readily usable EDA tools that help in creating designs where SI is maintained.
Ritchey explains, “There is no such thing as an ‘easy-to-use’ power integrity tool because there is no such thing as a simple PI problem. The closest there is the tool that was originally from Altera (This tool is now called the Intel PDN Tool 2.0). That tool has been used for thousands of boards. But it’s not adequate anymore when you get to these 100-amp devices. That’s because the problem extends way beyond the capacitors.”
“Now, IC developers are doing what IBM and Intel have done for decades,” continues Ritchey. “They have put all the capacitors that you need to get the part to work right on die and on package so clean power is delivered to these devices. The capacitors that we used to have on the PCB are now on the IC package. Component suppliers now tell you that you now only need bulk capacitors to support the switching supply.”
So what about the relationship between power integrity and EMI? Ritchey says, “Almost all of the EMI issues I know of come from a poorly-designed PDS because the ripple is too high and that ripple finds its way out of the box in several different ways most always on a signal wire.”
“Bottom line--if you do a good job designing your PDS, you have assessed all of the power integrity issues. Also, with a good PDS design, you get a huge leg up on EMI.”
As with other aspects of PCB design, there are certain ways in which a power integrity problem will be manifested. Ritchey explains, “From the SI point of view, the signals are going to be unstable. From an EMI point of view, you are going to see high EMI.”
He continues, “Right now the biggest problem that we see isn’t ripple. It’s that you can’t tolerate very much voltage sag. The voltage drop has to be really carefully managed because you don’t start out with much margin. For a chip running at .9 volts, you can’t have very much variance before you are out of the limit. For the last box that I saw, the challenge was to manage the DC voltage drop. To get enough copper in the middle of the board, there were four, one-ounce planes. These were not paired with signal layers because the thick copper was there for the conductors. The core of the board contained four heavy copper power planes.” The stackup for this board is shown in Figure 1.
So, today, which power integrity issues most impact designs? Ritchey states, “It’s pretty much across the board. Probably one of the most difficult is a cell phone because there might be 20 voltages and to preserve power you have things going from standby and active and, as a result, you have lots of transients.”
“In a big server, the PI problem comes from the hellish high currents that need to be delivered. High levels of integrations have allowed us to put some fantastic amounts of stuff in a ‘box’. And, of course, everybody is in a race to have more functionality in a “box” than the next guy. If you look at the teardown on the current X-box, that thing is really a supercomputer. In that design, they had both heating and PI issues.”
“PI has become a universal issue, and it dominates design now,” he adds. “I can’t think of anything else that is as bad.”
The challenge comes in not many engineers understanding power integrity.
Ritchey notes, “It’s not part of the engineering curriculum in universities. So, engineers read technical articles and go to industry conferences where there are certain tracks that are relative to PI. The book written by Eric Bogatin and Larry Smith, ‘Priniciples of PI for PDN Design—Simplified,’ is very good but you still need that hands-on perspective that is usually only found through private courses.”
“The reality is that PI is not going to go away and in fact, it is just going to get worse. People are going to have to pony up the money to go to specialized training classes. There is no other way to get the necessary knowledge.”
Ritchey continues, “I marvel at the people who think if they have bought a PI tool that they have solved the problem. The tool is only as good as the engineer running it. It calls to mind Gene Ahmdahl’s adage that a computer is an extremely fast idiot.”
He explains, “PI is not dependent on clock frequency anymore. We are already way past where discrete components work. The high-frequency stuff has to be engineered into the IC. The problem on the board is these very high currents have very little tolerance for error and the problem is growing.”
“We have been watching Vdd go down under a volt. The question becomes, how much farther down can it go? We are about to hit the limit where you can get the electrons to move through the transistor. Vdd won’t get any lower. Every time IC suppliers reduce the size of the gate, they put more transistors on the same size piece of silicon, and that causes the power to go up. And, as noted above, the currents keep going up.”
The question becomes, are we beyond the boundary of how many transistors there can be? Ritchey says, “Moore’s Law doesn’t really work anymore. (Note: Moore’s law states that the number of transistors in a dense IC doubles about every two years). It had to do with the length of the gates, and that is not as reliable as you might think.”
“The current technology says that we can get the transistor density up at least one more generation. We’re reaching the point where we have to ask why do we need more transistors on a part? We’re essentially making entire systems on a piece of silicon. The big win is being able to add the memory on the part with the processor. In that configuration, you get rid of the delay going out to external memory. The whole idea behind a cache goes away.”
He adds, “It’s staggering how quickly people take for granted what they are doing, that they can get a yield of parts that are good with that many elements. That is seriously good process control. If you look at a wafer fab now, there are no humans. The wafer failure rate is about 1 in 10 for a million parts for these very small process technologies. That’s pretty amazing.”
Power Integrity has become the dominant challenge in designing today's high-speed PCBs that have a lot of functionality, operating at very fast speeds, in ever-shrinking die sizes. Because power integrity spans across the entire system from the chip to the chip package to the board and the entire system itself, there are a number of factors that need to be considered in order to ensure that the design of the PDS is integrated across all those elements. Because power integrity is not addressed in university curricula, engineers have to seek a variety of knowledge sources and attend specialized courses offered in the industry to understand how to achieve and maintain power integrity.
If you've enjoyed this power integrity tutorial and you want to see how the best layout tools can help you tackle signal and power integrity problems, talk to an Altium expert today.
- Ritchey, Lee W. and Zasio, John J., “Right The First Time, A Practical Handbook on High Speed PCB and System Design,” Volumes 1 and 2.
- Ritchey, Lee W., Course content, “1-Day Power Delivery System Design,” training class.