Should You Place Teardrops on Differential Pairs?

Zachariah Peterson
|  Created: July 26, 2022
PCB Teardrops on Differential Pairs

One of the major factors impacting reliability of a PCBA is the use of teardrops on traces in the PCB. Teardrops are very useful, and some fabricators might require these in the Class III products they build with the intent of expanding the annular ring on a drilled hole. Like many aspects of reliability, the considerations also span into the signal integrity domain, particularly as more high-reliability products require greater data handling capabilities and run at higher speeds.

Because high-speed interfaces run with differential pairs, the question that naturally arises is:

  • Should you use teardrops on a differential pair?

This was a question posed to me by Mario Strano, one of our most recent podcast guests. This is an important issue in high speed design as teardrops essentially introduce an input impedance deviation at the input end of a via. Conceptually, I think this is an excellent question as PCB teardrops are important for reliability, and it reflects a recognition that teardrops can modify impedance. In this article, I’ll break down the issues present in teardrop usage on differential pairs and how these may affect impedance.

Why Teardrops?

First things first, I think it’s important to remember why teardrops might be placed on a differential pair (or any other trace) being routed into a via. During fabrication, when drilling holes for vias or other NPTH/mounting holes, it’s possible for the drill to wander between drill hits and slightly miss its drilling target. If there is a lot of wander, the drill could sever a connecting trace or pad from the via, and this could leave an open circuit connection after plating is applied.

Teardrops can be applied to help prevent any breakout that might sever a trace connected to a via pad. The idea here is to provide some additional copper to help prevent trace breakout from drilling during fabrication.

PCB teardrops
Teardrop added to a trace in a PCB.

Some IPC Class 3 fabrication houses will recommend teardrops, but this brings up the question of signal integrity on high-speed interfaces. How do these elements affect high-speed signals, especially on differential pairs? The question is important as the standard high-speed interfaces use differential signals, and more high-reliability products are incorporating these protocols.

Look to RF Design for Wisdom

Believe it or not, we can once again look to RF PCB design practices for guidance. What we have on these differential traces is a taper section, which RF engineers often use to match impedances. In fact, tapers are used as transition elements from microstrips to substrate integrated waveguides (SIW) and grounded coplanar waveguides. The impedance matching provided by these elements can be wideband and provides very consistent phase response between resonances for RF signals with moderate bandwidth.

For digital signals, there are three challenges we have to consider when examining how teardrops affect high-speed signals:

  • Bandwidth: All digital signals have broad bandwidth (theoretically infinite); the channel needs to transfer frequencies up to the Nyquist frequency limit.
  • Coupling: With differential pairs, we have a pair of coupled tapers, not just a single taper in isolation, and the coupling depends on the trace width and spacing.
  • Taper rate: The rate at which the teardrop tapers out to the via pad width determines the rate at which the single-ended impedance of one trace in the pair changes, and thus the rate at which the differential impedance changes.
  • Taper profile: Is the teardrop profile linear or curved? This will also matter for impedance matching and propagation.

Because of these three points, minimizing the impact of a teardrop on differential pairs requires selecting the appropriate taper width and length. However, because tapering out to a larger width decreases the trace impedance, you would want to ensure the input impedance into the via (only valid at high frequencies) is lower than the odd-mode impedance of the input trace prior to the taper.

For differential pairs, this means you need to control the spacing between the pairs and the taper rate/length along the teardrop. Let’s look at each of these points:

Taper Length

Next, we should ask, what taper length should be used in teardrops? Again, let’s go back to an RF system with a taper matching section. If you require a matching impedance with consistent return loss and no resonant behavior up to high bandwidths, then the taper needs to provide a smooth impedance transition up to the required bandwidth limit. The bandwidth limit in these tapers is defined by a phase transition, marked by constructive interference right at a particular resonant frequency (see the below).

Why should the bandwidth be limited? This is because the trace taper acts like a high-pass filter and it has some electrical length beyond which it will act like its own short section of transmission line if properly matched to the via. We can see where the taper becomes bandlimited by (again) drawing some insight from tapers generally. The example below shows a microstrip trace being tapered from a 50 Ohm trace to a 40 Ohm output with a teardrop on Rogers 3003 dielectric. We can immediately see that the bandwidth limit extends to higher frequencies when the taper gets smaller.

PCB taper behavior
Linear trace taper return loss spectrum for a 50 to 40 Ohm transition.

We only ever have perfect matching at specific frequencies, but there are mid-range frequencies where the return loss spectrum is flat. The above also assumes that the output side of the taper is perfectly matched to the via, but this may not be the case. If so, the return loss will be different and will be dominated by the reflection coefficient at the input to the via at lower frequencies.

Determining an analytical expression for the input impedance as a function of the taper rate in a teardrop is something I will look at in a 2nd part on this topic, so I will save it for later as it deserves its own article.

Spacing Between Teardrops

Spacing in differential pairs will partially determine the odd-mode impedance of each trace in the pair. If the traces taper into each other, the decreased spacing between the teardrop regions further reduces the impedance leading into the via. The effect on input impedance (and thus the S-parameters and channel compliance) will be influenced by both the spacing and the taper length, as well as the angle of the tapers.

PCB teardrops
Spacing between teardrops on a differential pair routing into vias.

If the spacing was already large, and you apply teardrops to the differential pair without angling them, there will be a larger-than-normal odd-mode impedance deviation because the spacing decreases along the length of the taper. The single-ended impedance will already decrease along the length of the taper, but the smaller spacing along the taper length will decrease the impedance even further.

If you’ve designed your differential pair without too small spacing (right side), and you’ve used a thin dielectric below your pairs (particularly for microstrip), then applying teardrops at a pair of differential vias will not have a big effect on impedance. The impedance was already dominated by the presence of ground. If you then angle the traces, you will see lower impedance deviation from the differential impedance looking into the via pair.

Design Rules

Based on the points listed above, we arrive at the following results for teardrops on differential pairs:

  • Larger signal bandwidths will require smaller teardrop taper distances
  • Try to angle out the teardrop sections to keep the edge-to-edge spacing constant
  • The final width should match the input impedance of the differential vias
  • The teardrop regions should be symmetric at the input and output of the via pair if possible

Unfortunately, stating “should match the input impedance of the differential vias/pads” in Point #3 is easier said than done. There is only one method I am aware of that gives any level of accuracy for differential via impedance calculations, and it starts from a calculation of the propagation delay through a pair of differential vias. Most single-ended via impedance calculators are totally inaccurate and do not produce anything matching experimental results from a TDR, so it does not make sense to start there. Also most via impedance calculators are not based on wideband models, so they will not consider propagation and mode excitation, so they will not produce a result that is accurate at high frequencies, which is exactly where you would need accuracy for high-speed signals!

Teardrops Aren’t Required For Reliability

Although teardrops are often recommended to ensure reliability, and some fabrication houses will recommend them on principle for any Class 3 product, they aren’t required for reliability. For example, in OpenVPX backplanes, you won’t see any requirement for teardrops, and I’ve never been asked to add them to one of these backplanes (either 3U or 6U). I bring up this particular open standard as its design requirements needed to ensure reliability are more conservative than what you would implement for Class 2 or 3 products, and they are deployed in some of the harshest environments (mil-aero).

As far as teardrop evaluation is concerned, simulations can be used to determine when the taper length and taper rate are too small/too large such that they start to impact the signal behavior. The key metric to examine is S-parameters looking into the teardrop section on the interconnect, specifically looking at S11 (return loss) to determine if there is an unacceptable impedance deviation. Some specialized electromagnetics solvers (HFSS, SIwave, Simbeor) will semi-automate the calculation of S11 with teardrops applied to a trace.

When you’ve qualified your PCB teardrop design and you’re ready to add these into your PCB layout, use the complete set of PCB design and routing features in Altium Designer®. The export options from Altium Designer also support other field solvers, such as the specialized Simbeor solver for interconnect evaluation and Ansys field solvers for SI/PI/EMI simulations. When you’ve finished your design, and you want to release files to your manufacturer, the Altium 365™ platform makes it easy to collaborate and share your projects.

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About Author

About Author

Zachariah Peterson has an extensive technical background in academia and industry. He currently provides research, design, and marketing services to companies in the electronics industry. Prior to working in the PCB industry, he taught at Portland State University and conducted research on random laser theory, materials, and stability. His background in scientific research spans topics in nanoparticle lasers, electronic and optoelectronic semiconductor devices, environmental sensors, and stochastics. His work has been published in over a dozen peer-reviewed journals and conference proceedings, and he has written 1000+ technical blogs on PCB design for a number of companies. He is a member of IEEE Photonics Society, IEEE Electronics Packaging Society, American Physical Society, and the Printed Circuit Engineering Association (PCEA), and he previously served on the INCITS Quantum Computing Technical Advisory Committee.

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