An impedance matching network is important for power transfer and preventing reflections. Rather than looking at power transfer, voltages, and currents, RF engineers normally look at S-parameters to evaluate impedance matching circuits as 2-port networks. In particular, the relevant quantities for impedance matching are normally insertion loss and return loss, which can be calculated using S-parameters for a 2-port impedance matching network.
Here, I’ll expand on a previous post and use the set of SPICE simulation tools in Altium Designer to design a simple LC network and simulate its behavior. For complex manipulations, you can easily export simulation data from Altium Designer and use it in any other analysis program. This will allow you to extract the broadband S-parameters as functions of frequency and easily convert them to insertion loss and return loss.
Impedance matching can be evaluated in a number of ways. For circuit elements placed in series, impedances are matched when the input and load impedances are complex conjugates of each other. In most practical situations, this only occurs within a narrow bandwidth, and you seldom get a broadband match without higher order filtration. The design goal is typically to bring insertion loss as close to 0 dB as possible (S21 → 1), and to bring return loss as far below some threshold as possible (usually below -10 dB, or S11 → 0).
The schematic below shows the impedance matching network we want to simulate. Here, the goal is to determine the frequency for optimal impedance matching by extracting the S-parameters, insertion loss, and return loss. Here, the source is set to 1 V amplitude, and frequency sweeps will be used to determine the insertion loss and return loss.
In the absence of the network, the power dissipated by the load resistor R2 can be easily calculated from our probe measurements. We want to simulate the power dissipated across the load in the presence of the matching network, which can be quantified using insertion loss and S21. We also need the power being input into the network, which can be calculated as the input current across R1 and the differential voltage across the (network + load) circuit. To evaluate the insertion loss and S21, you can use the following formula:
The return loss and S11 can be calculated by considering any reflection between the input impedance and the matching network + load impedance.
Here, we know the value of Z0 is the source impedance at the network input (50 Ohms), and we need to calculate Znetwork, which is the input impedance of the network (in other words, the network + load impedance). This will give us S11 and S21, which are two of the important parameters for this impedance matching network. Note that this network is reciprocal even though there is no symmetry in the circuit element arrangement. We always have the simple relationship between S12 = S21, but we may not have the same type of equivalence for S11 and S22. Because this is the case, you can determine the S-parameters for other ports by moving the source to the other side of the network and by placing the 70 Ohm load as the source impedance.
To get started, create a MixedSim profile and setup a frequency sweep. Here, we want to sweep the frequency from 100 MHz to 1 GHz. Run your simulation by choosing the option from the Simulate menu, or hit F9 on your keyboard. My AC sweep results are shown in the graph below. The top graph shows the power dissipated across the resistor, which will be used to calculate the insertion loss. This is calculated by simply selecting the r2[p] waveform.
The bottom graph shows the total impedance of the matching network + load, which will be used to calculate the return loss at the input. This must be calculated by taking the voltage drop across the entire network (netl1_1 waveform), and dividing this by the current flowing into the network (l1[i] waveform).
Here, the maximum power dissipation across the load is seen at ~448 MHz, so we would expect to see a minimum in the insertion loss spectrum at that point. To go further, you can use the waveform analysis features to calculate your results, or you can export your data as a .CSV file for use in an external program. I’ve decided to take my results into Excel for convenience. To do this, go to File → Export → Chart, and select the “Complex” option to export the real and imaginary parts of your data. The graph below shows the magnitude and phase of S11 and S21. These values can be easily converted to insertion loss using the formulas above.
Here, the impedance is most closely matched at ~445 MHz and S11 remains pretty flat over a ~200 MHz bandwidth, which is consistent with the power data shown in the graphs above. However, S11 is still quite high (minimum of 0.452, or -7 dB return loss), indicating some remaining mismatch. The way to proceed further is to iterate through different component values using parameter sweeps; the first inductor and the output capacitor are good places to start.
Another way to look at insertion loss, return loss, and S-parameters is to consider the impedance matching network as a filter with matched sources and loads. When designing the above network as a filter, you can determine the impedance or the transfer function using the same steps shown above. This involves removing the source and load resistors and simulating the T-network on its own. You can use the same procedure when simulating impedance matching for a capacitive or resistive load. In any case, if you want to ensure minimal power reflection, your goal is to examine the frequency of the impedance matching network at which conjugate matching to the load occurs.
The example shown here takes advantage of the pre-layout simulation features in Altium Designer®. When you use this powerful PCB design platform, you’ll have access to CAD tools that help you take your matching network designs and place them in a real PCB layout. You’ll also have the tools you need to import your data into a new layout and begin designing your PCB.