The Switching Behavior Of A Series-Terminated Transmission Line
Series-terminated lines and differential signals serve as the links in all CMOS devices. While I have written extensively on differential signaling, its operations and its benefits, I have not addressed the switching behavior of a series-terminated line. That is the purpose of this article.
The salient points about a series-terminated transmission line include the following:
- In this type of transmission line, a series termination is placed at the output of each driver.
- It provides the lowest power consumption for a high-speed logic signal.
- It is the lowest power consumption method because the energy is only consumed in the circuit when a logic line is switched from a logic 0 to a logic 1.
While the previous points appear to be very straight forward, understanding how a series-terminated transmission line works is vital to ensuring that the signals are being delivered properly to each receiver. Figure 1 is a typical 5V-CMOS driver with a 50-ohm transmission line connected to a CMOS receiver that is passive. This means that this device simply responds to the voltage waveform presented at its input. For the purposes of this explanation, CMOS receivers look like very small capacitors that can be considered to be open circuits. In this example, the line is 12” or about 30 cm long. In a PCB, energy travels at approximately six inches per nanosecond, so the line presented below is about two nanoseconds long.
Figure 1. A 5-Volt Series Terminated CMOS Transmission Line
Figure 2. Equivalent Circuit for the Transmission Line Shown in Figure 1.
As can be seen in Figure 2, capacitance and inductance are distributed along the length of the transmission line. These elements are the parasitics, and they determine the behavior of a transmission line with the ratio of inductance per unit length to capacitance per unit length. This determines the impedance of the line that is shown in Equation 1. Lo is the inductance per unit length, and Co is the capacitance per unit length. Using a tool such as a 2D-field solver (many field solvers are available as parts of various signal integrity tools) these two variables are determined for a particular transmission line.
Equation 1. Impedance as a Function of Distributed Capacitance and Inductance
When the driver in Figure 1 acts to move the logic level on the transmission line from a logic 0 to a logic 1, it must charge up the distributed parasitic capacitance of the transmission line. This is the primary power that is consumed by CMOS logic circuits. When the same driver acts to move the logic level from a logic 1 to a logic 0, that charge must be removed.
When a signal is sent along a wire or transmission line, the energy in it is in the form of an electromagnetic (EM) field. This energy will travel along the path and be reflected at the ends of the path forever unless it is absorbed by a terminating resistor or is slowly lost in the resistance of the conductor. If the ends of the path are open circuits, the reflected energy will be the same polarity as the incident energy. If the ends of the path are short circuits, the reflected energy will be inverted.
How the Charge On a Logic Line Moves it From a Zero to a One
The moment the driver starts to move the logic line from a 0 to a 1, the equivalent circuit in Figure 3 is formed. As can be seen, a voltage divider has been formed by the combination of the driver output impedance and the series termination in the upper part and the impedance of the transmission line in the lower part. When the series termination has been appropriately chosen, the combination of Zout and Zst will be the same as Zo. In this example, both will be 50 ohms, and the voltage at the input to the transmission line will be V/2.
Figure 3. Equivalent Circuit of Figure 1 as the Driver Switches from Logic 0 to Logic 1.
Figure 4 shows the voltage waveforms at the input to the transmission line and at the input to the receiver as time elapses.
Figure 4. Switching Waveforms for Circuit in Figure 1
This figure contains the following data points:
- The red waveform is the input to the transmission line, and the orange waveform is the input to the receiver at the end of the transmission line.
- As shown, the voltage level immediately after the transition from 0 to 1 is only half size.
- This is due to the voltage divider shown in Figure 3.
- This voltage level is often referred to as the “bench” voltage.
- Energy in the form of an EM field has been launched into the transmission line.
- This energy is charging the parasitic capacitance of the transmission line to the voltage level of V/2 as the field travels out the transmission line.
- After two nanoseconds (the electrical length of the transmission line) the line has been fully charged to V/2, and the EM field encounters an open circuit at the receiver. When such a field encounters an open circuit, none of the energy in the field is absorbed. Instead, it is reflected at the same magnitude it had when it was outbound.
- At the moment of total reflection, the voltage level on the end of the line is V/2. Since the voltage magnitude of the EM field is V/2, after total reflection the amplitude will be V. As can be seen, the orange waveform has an amplitude of V as soon as the EM field arrives at the end of the line. On the return trip, the parasitic capacitance of the transmission line is charged up to V. Once the EM field returns to the driver, it encounters the equivalent circuit shown in Figure 5.
Figure 5. Equivalent Circuit of Figure 1 as the Reflected Wave Arrives Back at the Driver
It should be noted that a voltage source, as shown in Figure 5 has zero impedance.
Since the sum of Zout and Zst is 50 ohms, and the voltage source is a short circuit, together they constitute a parallel termination that has the same value as the impedance of the transmission line. As a result, all of the energy in the EM field is absorbed, and the voltage level on the transmission line stabilizes at 5 volts which is an ideal logic 1 for this circuit.
Note: When a resistor has the same value as the impedance of a transmission line and is placed across the ends of that line all of the energy in the electromagnetic field will be absorbed by that resistor. There will be no further reflections, and this resistor is labeled as a parallel termination.
The Process of Switching from a Logic 1 to a Logic 0
When the circuit in Figure 1 switches from a logic 1 to a logic 0, the driver is tasked with removing the charge on the line capacitance that was put there to move it from a logic 0 to a logic 1. This happens as the driver level moves internally from 5V to 0V. As with the transition from a logic 0 to a logic 1, the equivalent circuit is as that depicted in Figure 3, but, now, the line is at 5V and the output impedance and series terminating resistor are connected to 0V. Thus, the voltage divider is working as it did before.
As a result of the preceding, the line voltage is moved to V/2 and the charge in the form of the EM field is removed from the line capacitance to this level as the energy moves down the line. (The voltage level of this transition is –V/2.) When the EM field arrives at the end of the transmission line two nanoseconds later, it encounters an open circuit and is reflected back down the line. After the reflection takes place, the line is at 0V. Two nanoseconds later the EM field arrives back at the driver and encounters the circuit shown in Figure 4, and it is absorbed.
As can be seen, the voltage waveform at the receiver (orange) is the desired, proper square wave logic signal (this is the goal of this signal path). This signaling method is known as “reflected wave” switching because the reflected wave creates the correct logic level as it makes its round trip along the transmission line. This is the lowest power consumption method of logic signaling because the current is only being drawn from the power system while the line is being charged. Once the line has been fully charged to a logic 1, the current draw goes to 0. This is the switching method that is employed with the PCI bus that is incorporated in most personal computers.
Also, note that the voltage waveform at the driver output is at an indeterminate logic state (V/2) for the time that is the roundtrip delay along the transmission line each time switching takes place. If loads are placed along the length of the transmission line, as is done with the PCI bus, they do not experience a “data good” condition until the reflected wave passes by them on the return trip. Therefore, clocking of data at these inputs must be delayed until data is good at all inputs. This is how data is clocked on the PCI bus as well as other bus protocols that rely on reflected wave switching.
What Happens When the Drive Impedance and Line Impedance Don’t Match?
The circuit shown in Figure 6 is the same as that shown in Figure 1 except that the series termination has not been inserted in series with the output.
Figure 6. 5-Volt CMOS Circuit Without A Series Termination
Figure 7 shows the switching waveform for the transition from a logic 0 to a logic 1. As is shown, the bench voltage is much higher than V/2. In fact, it is 2V/3 or 2/3 of the total of 5 volts or 3.33V. This is because the voltage divider in Figure 3 has the upper resistance of 25 ohms or Zout of the driver and the lower resistance or impedance of 50 ohms. This produces the 2/3 voltage level.
Figure 7. Voltage Waveform for Circuit in Figure 6
In Figure 7, the EM field is charging the line capacitance to the same value as before. When the EM field arrives at the receiver two nanoseconds after being generated, it is reflected doubling the voltage to 6.66V. As before, the EM field charges the line capacitance up to 6.66V. After another two nanoseconds, the EM field arrives back at the driver and encounters the termination shown in Figure 5. However, the parallel termination is 25 ohms, not 50 ohms. This means two things are happening. First, this time the voltage divider is 50 ohms on top and 25 ohms on the bottom. Because the series terminator value is zero ohms, the voltage is divided down. The second thing that is occurring is that not all of the energy is being absorbed.
As before, the amount of energy will double the voltage level at the receiver and travel back toward the driver. When it arrives at the driver, some of it is absorbed, and the rest is reflected inverted. This goes on until such time as all of the energy has been absorbed in the driver output impedance, and the logic level settles out at 5V. This can be seen in Figure 7.
Note: Delving into the above a bit further, when a parallel termination does not match the impedance of the transmission line across which it is placed, it will not absorb all of the energy reflected back down the TL. If the value of this termination is larger than the TL impedance, the energy will be reflected with the same polarity as the incident waveform. This is often called overshoot. If the value of this termination is smaller than the TL impedance, the energy that is reflected back two nanoseconds later will be inverted and be of the opposite polarity of the incident waveform. This is often called undershoot.
There are two problems with the waveform in Figure 7. First, the voltage goes 1.66 volts above Vdd. This excess voltage can cause logic failures or damage the receiver. Second, after the signal arrives back at the driver and is inverted, it will cause the logic 1 at the receiver to drop to below 4 volts. This diminishes the logic one to a level that could result in a logic failure. Neither of these situations is good. This is why a series termination is added to a circuit such as this.
Figure 8 shows the waveform when the signal switches to a logic 0. As can be seen, the same logic violations occur in this logic state.
Figure 8. Switching Waveform of Circuit Shown in Figure 6 With Both Logic Transitions
Along with differential signaling, series-terminated transmission lines serve as the links in CMOS devices. This type of transmission line provides the lowest power consumption for a high-speed signal. Understanding how a series-terminated transmission line operates and how it is charged up and down helps maintain signal quality and ensures that the line will perform as designed and as-built.
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- Ritchey, Lee W., and Zasio, John J., Right the First Time, A Practical Handbook on High Speed PCB and System Design, Volumes 1 and 2.