Differential Pair Length Matching: Best Practices for Signal Integrity

Conceptually, differential pairs are very simple, being just a pair of equal and opposite polarity signals running on two parallel conductors. In terms of signal integrity, differential pair routing becomes progressively more difficult when frequencies get higher. At the low end of the possible range of rise time values and frequencies, timing is the main constraint, while at faster rates we see issues with skew, mode conversion, and bandwidth limiting due to losses.

To ensure timing within some required margin, lengthening structures are applied along the length of the differential pair route. You may also have length tuning applied between multiple differential pairs and a parallel interface, such as CSI or specialty logic instantiated over LVDS. Of course, there are important requirements for successful link tuning, and the use of length tuning has an impact on signal integrity, which is normally not considered until channel qualification.

To help ensure you reach success with linking structures, I'll provide some simple guidelines that can help you eliminate signal integrity problems from length-tuning structures in your PCB. While it is important to provide link tuning structures in your design, sometimes judicious use gives you better results, especially when designing for multi-Gbps interfaces.

The Rise Time Window

All length tuning structures are implemented not just to equalize the length of the traces in a differential pair. Really, it is to provide delay such that the opposite polarity signals on each end of a differential pair are aligned in time. Differential receivers are crossing detectors, so the timing requirement is that the two signals must be switching at the receiver at the same time. This gives us a timing window, which is a bit less than the rise time, and that can be set equal to a length mismatch window as shown in the graph below.

Now, whenever you set up a length mismatch or timing mismatch constraint in your PCB layout, the PCB editor would use the physical length you have set down for the traces in your PCB to determine a length mismatch. If the propagation delay for the signals on the interconnect is known, then the corresponding timing mismatch can also be determined by the PCB editor. This is then checked against the length constraint in real time as you apply the length tuning structure.

How Close Should You Tune Trace Lengths?

There is no specific value required for differential pair length tuning. Technically, any remaining timing mismatch that is less than the timing window (as illustrated in the above graph) can ensure the interface is fully functional as long as there is no additional jitter seen at the receiver (see below for details on this).

This leaves a lot of room for your differential pair length tuning margin. For example, let us suppose that we have a timing window of 100 ps; if we have loosely spaced traces in a differential pair routed as striplines on the Dk = 4 substrate, then the allowed length match will be:

ΔL = (1.5e11 mm/s)*(100 ps)*(39.37 mil/mm) = 591 mil

Obviously, this is a very generous amount of length mismatch, and you would be able to accommodate this mismatch easily in any CAD system.

Some component datasheets will state a fixed value for maximum allowed length mismatch and will not mention a timing mismatch at all. If you ever see a nice round number for allowed length mismatch, such as 100 mils, it is probably an arbitrary value. Furthermore, as we saw in the above calculation, the link mismatch depends on the dielectric constant of the substrate material, i.e., the signal propagation velocity, but the datasheet may never mention a qualifying dielectric constant for their specification.

Rather than using these arbitrary numbers from data sheets, or trying to justify a length mismatch based on dielectric constant or data rate, try to get the length mismatch as small as possible by applying various types of length tuning sections.

Altium Rules for Applying Differential Pair Length Tuning

If you route a differential pair and you find that you do need to apply link tuning to the route, there are three very simple rules that help prevent ensure signal integrity:

1. Start by designing the pair with loose coupling and preference for a thinner PCB laminate
2. Keep length tuning structures as short as possible
3. Apply the length tuning exactly where skew arises
4. Try to get the length mismatch as close as possible to zero

Principally there are two signal integrity problems these guidelines address: these are mode conversion, and jitter or skew from fiber weave.

Mode Conversion

The first three rules are all intended to help prevent mode conversion within the differential pair length tuning structure. Length tuning structures help align signals in time by enforcing a delay, but they represent an inherent differential impedance discontinuity along the length of the route. In particular, the length tuning structure will have its own input impedance, which will be a function of frequency.

Suppose you have a long route and you need to apply a large amount of length tuning to restore signal edge rate timing along the differential pair. Where should small sections of length tuning be placed? The answer is in rule #3, such as in the example shown below. These small sections of length tuning structure are applied right at trace bends and are only made as long as is absolutely necessary. One of these sections can be placed at each bend along this route.

In some cases, you have no choice but to place the length tune section just after the region where the mismatch occurs, such as in the example shown below. In this example, there are 6 differential pairs being routed as striplines; the bends in the breakout region create some skew, but once the pairs complete breakout there is enough room to apply the length tuning regions. These are small sections that have been placed reasonably close to the breakout region.

Do you always need to make differential pair length tuning structures extremely short? It all depends on the required channel bandwidth. Mode conversion created by length tuning structures is a bandwidth limiting effect, and so your channel design should account for this based on the bandwidth required at the receiver.

Because this is all based on input impedance, the differential pair length tuning structure will have the following properties:

• Longer length tuning structures will exhibit more mode conversion at lower frequencies
• Larger amplitude in the tuning structure may create more mode conversion

Following design of the differential route, the channel should be simulated to verify channel bandwidth and mode conversion.

Jitter

The fourth rule listed above addresses jitter and skew from fiber weave. These two effects will always be present; reducing the length mismatch to zero does not eliminate jitter or leftover skew from the fiber weave, rather it ensures your available length mismatch margin can accommodate some amount of skew/jitter.

If the signal experiences appreciable jitter, the bus can still work as long as the jitter occurs within the timing window; the same applies to skew from the fiber weave. This can occur even when the trace lengths are perfectly matched; this is why it’s best to match lengths/delays as close as possible in your CAD tool: there will always be a little bit of jitter and it should only occur in the timing window. Jitter is classified as random, pseudo-random, and deterministic, and each can be caused by a number of factors in your board layout. Major sources of jitter include:

• Transient ringing on the PDN
• Spurious frequencies in a clock synthesizer (PLL)
• Crosstalk
• Reflections as part of intersymbol interference

Jitter can be measured directly in an eye diagram or determined from a simulation, such as the oscilloscope readout shown below.

As was mentioned above, the same applies to skew, even when there is absolutely no jitter present in the channel. Skew could arise from fiber weave, which will accumulate over long routes and will cause eventual misalignment of the differential signal. This is normally solved with mechanical spread glass laminates, which will carry greater expense over low-cost FR4 with open weave styles.

Solving Length Mismatch in Differential Pairs

Whether you use time or length as the basis for your design rule, your PCB editor will take the same approach and use the physical length in your PCB layout to determine compliance to a length mismatch rule. Trombone, accordion, and sawtooth meandering are all useful options for differential pair length tuning sections to keep your signals timed together. This will not only match trace lengths in the pair, but will also ensure common-mode noise can be reliably eliminated at the differential receiver.

The points about timing listed above only apply within a differential pair, and not between multiple pairs. Multi-pair interfaces have their own timing restrictions that must be met, with often being routed with a source-synchronous clock. When inter-pair timing needs to be enforced, look at the requirements for your interface and create a separate design rule for matching between differential pairs.

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