Differential Pair Length Matching: Best Practices for Signal Integrity

Zachariah Peterson
|  Created: April 8, 2020  |  Updated: September 25, 2020
Length matching with differential pairs is like walking a tightrope

Take two signals and send them down a parallel bus or differential pair. How can you be sure the downstream receiver will latch to your signals? If your signals don’t arrive at the same place and at the same time, then gates in your receiver won’t latch at just the right moment. This delicate balance can be like walking a tightrope across a cliff, and it can be difficult to maintain differential pair length matching by eyeing your trace lengths.

If you’re routing a differential pair in a straight line between a driver and receiver, it’s easy to maintain length matching. As long as you route the traces side-by-side consistently, you can immediately see whether tight matching will be maintained. Real situations in a PCB are seldom this simple. Here’s how you can determine the permissible length/timing mismatch in your differential pairs and how your routing tools can help you correct length mismatch.

Visualizing Length Mismatch

Differential signaling is all about synchronization. In order to ensure near perfect noise cancellation at a receiver, you need to ensure your signals are in perfect synchrony. You can often get close to having your differential pairs being perfectly length matched, but designers often try to limit any length mismatch below some upper limit. Your length mismatch and timing mismatch are related by the propagation delay, and you can use an acceptable timing mismatch alongside jitter to determine the acceptable length mismatch for your differential pairs.

Differential Pair Length Matching vs. Timing Matching

Length matching and timing matching are intimately related due to the finite signal propagation speed. Normally, your differential signaling standard will specify permissible timing mismatches (usually in absolute units or as a fraction of UI). However, the important point here is to convert the allowed timing mismatch to a length mismatch when routing on a particular substrate, or vice versa.

The graph below shows a simple example of what happens with LVDS when the two ends of a differential pair are mismatched. Here, the signals switch polarity to indicate a HIGH or LOW state at the receiver. Due to the length mismatch, the signals switch at slightly different times. There is a time window between the two signals, which is easily calculated using the signal velocity and the length mismatch Δl. In this example, the delay between the signals is only 300 ps.

Differential pair length matching with LVDS signals
Relationship between length and timing mismatch with LVDS

The implication here is that any common-mode noise that is present in the time window Δt will not be fully cancelled by the receiver. When the propagation velocity is larger (i.e., when the real part of the dielectric constant Dk is smaller), the length window is larger. For a specified timing mismatch on one substrate, one might prefer to use an alternative substrate with a smaller dielectric constant, which would increase the allowed length mismatch.

What About Jitter?

If the source has appreciable jitter during driving, then you’ve effectively increased the mismatch and delay difference between the two signals, even if the trace lengths are perfectly matched. Jitter is classified as random, pseudo-random, and deterministic, and each can be caused by a number of factors in your board layout. Prime causes of jitter include transient ringing on the PDN, spurious frequencies in a clock synthesizer (PLL), and parasitic resonances on the output from a switching regulator. In general, your jitter should not exceed your allowed timing mismatch unless you want to see high BER values. You can measure the different sources of phase noise on the output from a component in the frequency domain.

Eye diagram and differential pair length matching
You can see the effects of jitter on differential channels in an eye diagram.

Solving Length Mismatch in Differential Pairs

The fact that the important quantity determining noise immunity is the signal timing mismatch has motivated the use of delay tuning for differential signals. The typical method for matching timing in a differential pair is to match the lengths of the two lines at the source of the interconnect, also known as phase matching. The two points at the beginning of the pair might be weakly coupled, but adding or removing some copper at the source end allows you to match pair lengths while ensuring common-mode noise can be reliably cancelled at the receiver. Trombone, accordion, and sawtooth meandering can be used to add additional length to one end of the pair in the coupled region.

In addition to timing jitter, your signals might have a slower rise time, such as might occur in a lossy substrate. In other cases, where you choose to route on something other than FR4, the allowed length mismatch will be different, depending on the substrate’s dielectric constant. Be sure to keep this in mind when you are floorplanning your differential pairs, selecting components, and choosing a substrate material.

How an Integrated Electromagnetic Solver Aids Length Matching

If you have access to routing tools with an integrated electromagnetic solver, your routing tools can automatically compare delay in a length matching segment to your permissible timing mismatch. This type of routing tool will automatically calculate the propagation delay on an interconnect during length matching, including for differential pairs. It also accounts for the complex geometry used in length matching segments and parasitic inductance and capacitance along an interconnect.

The interactive routing and differential pair length matching features in Altium Designer® include an integrated electromagnetic solver, giving you instant access to delay tuning as you route your board. These features run in the background and load at the click of a button. You won’t have to export your design to an external program to access these features.

Now you can download a free trial of Altium Designer and learn more about the industry’s best layout, simulation, and production planning tools. Talk to an Altium expert today to learn more.

About Author

About Author

Zachariah Peterson has an extensive technical background in academia and industry. He currently provides research, design, and marketing services to companies in the electronics industry. Prior to working in the PCB industry, he taught at Portland State University and conducted research on random laser theory, materials, and stability. His background in scientific research spans topics in nanoparticle lasers, electronic and optoelectronic semiconductor devices, environmental sensors, and stochastics. His work has been published in over a dozen peer-reviewed journals and conference proceedings, and he has written 1000+ technical blogs on PCB design for a number of companies. He is a member of IEEE Photonics Society, IEEE Electronics Packaging Society, and the American Physical Society, and he currently serves on the INCITS Quantum Computing Technical Advisory Committee.

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