Channel Bandwidth: The Right Way to Qualify High-Speed PCB Interconnects

If you read high-speed PCB design guidelines from semiconductor manufacturers and non-experts, they always talk about the use of rise time to analyze signal integrity. Signal rise time is important, as it determines things like EMI, crosstalk, and delay tuning tolerances. If your design is operating at gigabit-per-second data rates and faster, your rise time typically ends with delay tuning, and all other signal integrity factors are analyzed in the frequency domain.

Pro designers think in terms of a simple metric: bandwidth. Whenever bandwidth is mentioned, novice designers immediately bring up knee frequency as a measure of signal bandwidth. This is completely wrong. All digital signals have infinite bandwidth, even after being attenuated by a physical transmission line.

But when designing at multi-Gbps speeds, the relevant bandwidth is the channel bandwidth. In other words, this is the frequency range through which a transmission line allows strong transmission of signals with minimal attenuation or reflections. A basic understanding of how bandwidth is determined from S-parameters is mandatory for anyone wanting to work beyond 1 Gbps.

How to Quantify Bandwidth

Bandwidth can be determined from a frequency range measurement. All digital interfaces have a bandwidth requirement, meaning the physical channel connecting a transmitter and receiver must admit a certain amount of bandwidth within a specific range of frequencies (from DC up to some maximum frequency). Stated another way, a bandwidth specification can be described as follows:

• A physical channel must not absorb or reflect too much power within a frequency range from DC up to some maximum frequency.

We can verify that a physical channel (i.e., a transmission line) provides enough bandwidth by looking at an S-parameter plot. There are other parameter plots we could use as well, such as the transfer function or T-parameters, but the most common is the use of S-parameters.

Consider the return loss plot for a pair of differential blind vias shown below, which rises to its -10 dB limit at about 70 GHz. We could say this channel (blind vias connected to impedance matched differential pairs of 100 Ohms) has 70 GHz of bandwidth.

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When looking at an S-parameter plot or a transfer function plot, we need to have a consistent definition of what determines the maximum bandwidth of a channel. For an S-parameter plot, a de facto bandwidth limit is the lowest frequency where the return loss reaches up to -10 dB. In the example plot above, the transmission line in question would be able to provide 23 GHz of bandwidth based on the return loss spectrum.

This is not a universal standard, and one should note that different interfaces will have different requirements for the transmission line used to transport a signal. For example, in some research by the 802.3 working group on 224G PAM-4 signaling, the bandwidth limit is defined at -15 dB return loss rather than -10 dB return loss.

How Does Channel Bandwidth Relate to Data Rate?

While it is true that we generally do not categorize digital interfaces as high-speed based solely on their data rate, channel bandwidth does relate to the data rate that a channel can transport between two components. The maximum data rate that a channel can transfer is related to the channel’s bandwidth by the Nyquist rate formula. This formula does not have the same meaning as it does when applied to ADCs; it has a different meaning when discussing the communication of digital data through a physical channel.

The relationship between bandwidth and data rate is based on the number of logic levels available to the interface during each clock cycle. This formula is:  

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In this formula, we assume that rise time is infinitely fast and that bandwidth is defined as a hard cutoff at the bandwidth limit frequency. In theory, this would mean signal integrity for digital data could be predicted using only a return loss plot, but this is not true in practice. Because losses are functions of frequency and slowly degrade the signal during propagation, we have to examine the behavior of the signal at the receiving end of a transmission line.

This is why we use an eye diagram to visualize the signals at the receiver. The edge rate and noise at each logic level in the eye diagram will determine the bit error rate (BER). As long as the bit error rate is low enough, the channel can be deemed to be transferring enough of the signal power throughout its bandwidth for the interface to function correctly.

Do We Even Care About Signal Bandwidth?

The answer is both yes and no. Signal bandwidth is technically infinite, so no matter what you do, your digital I/O is always trying to source frequencies spanning out to infinity. As a signal propagates through the channel, that power is lost with greater attenuation at higher frequencies. What comes out of the channel and interacts with the receiver is still a signal with infinite bandwidth, but the high-frequency content is reduced due to dielectric losses, copper losses, and radiation losses.

So with that in mind, let's look at the complete list of steps detailing what happens as a signal starts at a transmitter and reaches a receiver.

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1. The signal is dropped across the output pin into the physical channel, and the voltage rises. At this point, the rise time is the fastest it can possibly be.
2. The signal begins traveling along the transmission line. During travel, power at high frequencies is attenuated, which reduces the edge rate.
3. The signal reaches the receiver, and some power above the receiver's bandwidth gets reflected. The signal interacts with the receiver input and rises to its final voltage.

Because losses are reducing the high-frequency content of the signal, the edge rate slows down during propagation. Read this related article for an extreme example of edge rate degradation.

Because we always define high-speed PCBs by rise time, and because of overgeneralized formulas like the knee frequency formula, this creates a perception that we need to somehow use signal bandwidth to design things in a channel. The most common instance is the use of a signal rise time to calculate a critical length, something which is a pointless exercise and an excuse to not calculate trace impedance. The problem with this is very simple: in a long transmission line, the signal rise time has no relation to the receiver's knee frequency because the signal has not reached the receiver's input pin! Therefore, concepts like rise time and knee frequency should not play any role in designing a high-speed PCB with Gbps or higher channels.

Rise Time - What is it Good For?

Absolutely nothing!

I’m joking of course… rise time is an important tool for estimating or understanding some aspects of signal integrity and EMI/EMC. This includes:

• Estimating the magnitude of crosstalk
• Understanding the space and impedance resolution of TDR measurements
• Understanding test load capacitance specifications 
• Identifying sources of EMI
• Predicting the minimum scope bandwidth needed to accurately measure a signal

The above list only specifies how rise time influences signal integrity and measurements, not an actual design task. In reality, there are surprisingly few situations where the signal rise time needs to actually be used directly as an aid for designing a transmission line for a high speed PCB. These reduce to two instances:

• Time delay matching in differential pairs
• Series or parallel impedance matching of buses without an impedance specification

The first instance is very straightforward and does not require much more than an estimate of the rise time, which can be taken from a datasheet for a given test load capacitance. The second instance only applies to very few situations, such as fast GPIOs, SPI/QSPI/PPI, or some specialty logic. This would be based entirely on a critical length analysis.

The Takeaway

In summary, most discussions of “rise time” bandwidth in regards to signal are often discussing the response of something driven by a step function, not the infinite bandwidth of a digital signal. For high-speed designers, the takeaway here is very simple: because we use this concept of channel bandwidth to evaluate the design of a transmission line, you will need to verify signal integrity throughout the channel bandwidth. The use of rise time does not enable this important approach.

This is not to say that simulations based on rise time are not useful, just that they do not capture the full picture of channel behavior. I mentioned eye diagrams above, but there are two other important instances where rise time-based simulations are useful:  

• Time-domain reflectometry (TDR) simulations
• Evaluating model causality in the time domain

I've discussed causality in another article. In a future article, I will look at how to understand and use a TDR trace as part of high-speed PCB design and signal integrity.

For now, my advice to designers is simple: the rise time concept as a tool for understanding the need for impedance matching is only applicable on a few fast single-ended interfaces. All other instances involving impedance-controlled differential pairs do not use a concept of rise time at all except to understand delay tuning/length matching. For these faster serial differential channels, always design to the target impedance and understand how to qualify the channels using bandwidth as your guiding metric.

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