Through Thick And Thin — How Do You Get High Current Into a High Speed PCB?

In various blog articles, we have described the aspects of board design and fabrication that can add increased complexity and cost to high-performance PCBs. One of those aspects is in regards to how thick PCBs need to be, especially as it relates to the amount of copper needed on a board and the laminate thickness.

Up until the current generation of boards, which are typified as being high speed PCBs with high current, we were fine with having ½ oz./sq. ft. copper for signal and plane layers. But, the typical large currents in today’s high speed PCB designs require a different approach. This article will describe the stackup requirements associated with these very large current PCBs and how to design them so that they can be readily manufactured properly.

Layers to Support High Current in High Speed PCBs

To see how plane layers play an important role in high speed PCBs beyond just providing interplane capacitance, it helps to look at some typical stackups in modern PCBs. Figures 1 and 2 show the same 22-layer board stackup. Figure 1 is for a PCB that is not designed to accommodate high current. 

Figure 2 shows the same 22-layer stackup, but it has been modified to accommodate large currents. Support large current. Note that Figure 2 shows a stackup that is more desirable for a typical high speed PCB; there are no adjacent signal layers, the Dk value for each laminate is lower, and the traces in each layer are less wide.

If we were to go back ten years, the stackup in Figure 1 reflected the then state-of-the-art high speed PCB design, which was driven by signal layers. This stackup has ten signal layers, five Vdd planes and five ground planes. Now, we have migrated to the stackup in Figure 2 where more power planes are required to support the high currents being drawn by high pin count ICs in modern digital systems. This stackup has eight signal layers, six Vdd planes and six ground planes. Prior to today’s iterations of ICs, a high current was 30 A. Now, it is common to have one high speed IC that draws 160 A at only 0.9 V, and there is no margin for a voltage drop. So, we have gone from agonizing about getting all the signals right to agonizing about getting all the power right (which is one of the reasons why PDS design is such a crucial part of every high speed PCB being designed today).

Prior to high pin count component packages, it was standard practice to have ½ oz./sq. ft. copper for both signal and plane layers as is depicted in the stackup in Figure 1. Today, the stackup in Figure 2 must be used. In Figure 2, two of the signal layers have been converted to planes such that they are twice as thick and have 1 oz./sq. ft. copper each. Thus, there are four power planes in a row, and they are all one-ounce copper.

The extra copper in the power plane is to get the very high current through the pins into BGA components. The PCB is perforated with all those holes for device leads, so extra copper must be used in the plane layers to ensure there is enough copper to accommodate the via holes created by the high number of BGA pins.

So, with the addition of more and thicker plane layers, does it mean that PCBs are getting thicker and therefore more expensive? The answer is no. This is due to the transition from parallel buses to differential signaling. Differential signaling requires far less wire space than parallel buses, so the overall number of signal layers has been reduced. The extra signal layers are then allocated to plane layers with 1 oz./sq. ft. copper.

The Science Behind it all

The aforementioned high-pin-count devices in high speed PCBs must be connected using vias to access the internal plane layers of the PCB. The proper design of the hole along with the pad stack results in high-yield power planes while preserving the quality of the very fast signals that are routed through these areas. A typical power plane structure results when a high-pin count BGA is placed on a multilayer high speed PCB. Figure 3 shows a trace routed over a typical hole pattern created in a power plane by a BGA.

The clearance holes in the power planes allow room for holes drilled through the PCB when creating the vias needed to connect to the BGA pins. The pad or hole in the plane is the minimum distance that the copper in the plane and trace layers must be kept away from the drilled hole. It’s imperative that the traces not pass through these clearances. Stated another way, room for traces between pins is the width of the web between the planes. If we want to fit two traces between pins on a high-density BGA, this web will need to be as wide as the two traces plus the space that separates them. The factors that must be taken into account when designing a pad stack for high pin count devices to ensure board manufacturability include: 

• Making sure the drilled hole is large enough to ensure proper aspect ratio for reliable plating. 
• Making sure the capture pads are large enough to allow for drill wander and still provide a minimum annular ring. 
• Making sure the clearance holes in planes are large enough to meet minimum insulation requirements. 
• Making sure the clearance holes in the planes are small enough to leave an adequate web between adjacent holes over which the transmission lines must travel. 
• Making sure the thermal ties to planes are small enough to ensure proper thermal isolation and large enough to ensure a reliable electrical connection. Thermal ties and their recommended implementations were addressed in my article: Pad Stack Design And Fabrication—Part 2, Thermal.

Summary

Today’s high pin count devices offer a great deal of functionality in one device mounted on a high speed PCB. In order to accommodate all of the clearance holes for these devices, extra copper has to be added to the PCB plane layers to allow high current through pins on a BGA. Proper design of these holes along with the right pad stack will ensure these devices will work as required for the life of the product. 

Have more questions? Call an expert at Altium or continue reading about Net Clearance Rules For Greater Flexibility In PCB Design.

References:

1. Ritchey, Lee W. and Zasio, John J., “Right The First Time, A Practical Handbook on High Speed PCB and System Design Volume 1.