High-Speed PCB Design: Just How Fast Is Fast?
Table of Contents
As noted in several previous blogs, these days, “high-speed PCB” is pretty much ubiquitous in our industry. And, as cited, we always say that regardless of the end product or implementation every PCB is high speed by virtue of the IC technology incorporated in it. A few years back, we started saying that what was important was the edge rates of the components, or more specifically, the interconnections between the component edges and the boards. That’s actually how we arrived at the name for our business, Speeding Edge. It is an amalgamation of the terms “bleeding edge” and “high-speed edge rates” as exhibited by the component interconnections on PCBs.
It’s worth revisiting what the evolution of the term “high speed” means and how it has changed over the years. This article will discuss the history of high-speed PCBs, what we really mean when we say a PCB device is high-speed and some of the rules-of-thumb that are inappropriately applied to the high-speed PCB design process. Valuable resources regarding the information on high-speed design principles will also be discussed.
High-speed PCBs have actually been around for a long time dating back to the mainframe computers designed and built by companies such as IBM and Cray. But that was a pretty isolated niche relative to the rest of the PCB industry. For the rest of the world, high speed became an issue of concern in the early 80s when TTL got fast enough that paths became long. And that’s how we define high speed with respect to signal integrity; a PCB is high-speed when the signal paths are long relative to the rise times, and a path becomes long when the signal can reflect off the open end and cause problems.
In terms of precise mathematics, if the rise time is a nanosecond, every path that is 3” or longer can fail because of reflections. Note: 3”=7.5 cm and 6”=15 cm. You convert rise time to length by finding out the velocity of the path. In PCBs, this equates roughly to 6” per nanosecond. This is the starting point.And, how often that occurs or what the clock rate is has no impact on the determination.
As Lee Ritchey, President and Founder of Speeding Edge notes, “I have seen designs fail on a ‘power on’ reset line. This happens when you turn on the power. People would judge this as noncritical because it didn’t happen often. The world has this habit of judging fast based on the clock frequency and that’s where they get in trouble. “
As an example, some years back we troubleshot a pulse oximeter that had failed. The company that designed the product determined that the product was “slow” because it had a 1MHz clock. But it didn’t work because the memory portion of the design had a 350 picosecond rise time.
So where are we now? The last data that we looked at from Micron Technology for their memory components said that the slow edge was 100 picoseconds and the nominal edge was 50 picoseconds. The fast edge was not specified. If we begin with a nanosecond, the slow edge is 1/10 of that which means that for the slow edge a path 3/10 of an inch long can exhibit failure from reflections. In this scenario, there is no product that is not fast no matter the clock frequency.
Product designers today still get in trouble when they assume that because their final product implementations are not “fast” that, by default, that means the product is not high speed. And, there are five areas where people tend to make mistakes. These include:
Not following signal integrity rules. This encompasses not controlling impedance, not using proper terminations and utilizing app notes as design guides. A lot of excuses for failed designs begin with “I followed the app note, the product doesn’t work.” (Many applications notes do not contain valid signal integrity advice.)
Having a lot of tech product ideas that come from people who don’t understand the technical
rules. In the past 30 years, there have been a lot of product ideas originating with computer science engineers who don’t have any training in signal integrity.
Grabbing a bunch of rules-of-thumb and applying them to the design process without understanding how things really work.
And, as noted in several previous articles, in high-speed designs, the biggest and most critical challenge today is designing a properly functioning PDS.
When it comes to high-speed design considerations, some of the biggest problems are derived from using rules-of-thumb that have no basis in good engineering practices. The three most common ones associated with high-speed PCB design are:
The 20H rule
The 3W rule
The stitching vias rule
The 20H rule is one of a group of about a dozen made up rules that originated in the early 90s. This rule alleges that if you recess Vdd from the ground plane by the dimension that is 20 times the separation or “H” (which stands for height between the two planes), you would reduce EMI. This rule was put to the test at two different universities by students who built test boards to discern the validation of the rule. One test board was built with Vdd and the ground plane being flush while the other was built using the 20H rule. The plane pair was excited with an RF generator and checked with a near-field probe to determine if there was any EMI escaping from the edge. The first thing that was learned was that the magnitude of the radiation that would escape was so small that it would never cause an EMI problem. Further, what little radiation that did escape was worse when the 20H rule was applied versus the Vdd and ground plane being flush. The papers concerning these tests are References 2 and 3 at the end of this article.
This rule, which is based on another arbitrary decision, states that in order to control crosstalk between parallel traces routed on the same layer, a minimum spacing between traces centers of 3-W should be kept. The thing to bear in mind is that crosstalk is not a function of trace width. Instead, it is the unwanted interaction between signal wires or traces travelling in parallel (also referred to as coupling), and it’s a function of two things:
How far apart are the two edges?
How high are the traces above the nearest plane?
The only way to determine these two factors is through the use of a simulator. This is a very straight forward analysis that takes about two minutes to conduct. However, it’s important to note that until you know how much the victim line can tolerate in terms of coupled noise, you cannot begin the analysis process.
As noted in my blog on guard traces (Guard Traces: Hit or Myth?), it’s alleged that stitching vias control crosstalk and are a barrier to the electromagnetic field. Stitching vias are implemented by putting a guard trace between two other traces and then periodically putting a via from the trace to the ground plane underneath. The truth is that if the use of stitching vias was required in order for a product to work, none of today’s Internet products—servers, bridges and routers--could be manufactured. Mechanically, there simply isn’t enough room to separate the thousands of traces that are in these products.
And, as Lee Ritchey states, “I have found that every rule that is valid has a straightforward proof. If the person citing the rule can’t give the proof, you ought not to use it.”
One of the challenges that we are facing in the industry is the plethora of bad information that is circulating in various public domains (trade publications, the Internet, books by “so-called” experts). The real challenge is that within these information resources, there sometimes ends up being a lot of information that is correct but paired with information that is not. The difficulty lies in discerning between the information you can trust and that which you cannot.
There are two really good information forums that are available that contain valid design rules: The IEEE forum database and the SI-LIST reflector. The SI-List was launched in 1994 with 30 members comprising the charter e-mail list. Through it, engineers can post questions, answer questions, participate in debates or listen to the “chatter.”
To subscribe to the SI-List go to http://www.freelists.org/webpage/silist. To view the archives of postings, go to: https://www.freelists.org/archive/si-list/
The IEEE provides access to publications, conferences, technology standards and professional and educational activities to promote the advancement of engineering disciplines. It is possible to join the IEEE as an engineering professional or as a student.
By virtue of the technology incorporated on it, every PCB designed today is high-speed. Understanding what high speed is and which information constitutes a valid high-speed design approach will ensure that you are creating a product that will work right the first time.
Ritchey, Lee W. and Zasio, John J., “Right The First Time, A Practical Handbook on High-Speed PCB and System Design, Volumes 1 and 2.”
“Effects of 20-H Rule and Shielding Vias on Electromagnetic Radiation From Printed Circuit Boards,” Huabo Chen, Student Member, IEEE, and Jiayuan Fang, Senior Member, IEEE Dept. of
Electrical Engineering, University of California at Santa Cruz, Santa Cruz, CA 95064. “Radiation from Edge Effects in Printed Circuit Boards (PCBs)”, Dr. Zorica Pantic-Tanner & Franz Gisin, presentation at the monthly chapter meeting of Santa Clara Valley Chapter of IEEE EMC Society, May, 2000.
Would you like to find out more about how Altium can help you with your next PCB design? Talk to an expert at Altium or discover more about the best high-speed design tools in Altium Designer®.