How to Place PCB Cavities for Embedded SMD Parts

| Created: May 24, 2023 | Updated: June 7, 2023

Types of Embedded Cavities in IPC Standards
SMD Components in PCB Cavities
Configuring Cavities in Your PCB Layout
Fabrication Notes for Cavities

When we talk about embedded, we aren’t always talking about embedded software. Components can also be embedded in a PCB by placing a cavity region in the internal layers. Cavity regions in a PCB allow component placement, filling with copper for an embedded heatsink, or inset placement below a surface layer in a PCB. If you want to free up space on surface layers, or just lower the profile of your PCBA, cavities are one option that could help.

Types of Embedded Cavities in IPC Standards

The newest revision of the IPC standards for rigid PCBs defines three types of embedded cavities and their acceptability criteria. The following cavity types are defined in IPC-6012F:

Type 1	A cavity that has no internal copper plating or metalization
Type 2	A cavity with copper on the top/bottom of the cavity, or on the walls (not both). This is the most common type of cavity.
Type 3	A cavity with copper plating on the walls, and with copper plating on the floor region.

Cavities can have copper internally, such as traces and pads, making them Type 2. If there is also some plating along the wall, such as partially plated walls, then this would be a Type 3 cavity.

Cavities can also be totally filled with copper, sometimes referred to as a copper coin (or “coining”). This is normally done so that the region internal to the PCB can act like a large heat sink; when placed under a component, it will provide significant heat transfer to the interior of the board. If the coin is then connected to a plane or placed near a large plane, it will provide significant heat transfer away from a hot component. This can also be used with bonding the assembly to the enclosure, so that now the coin + enclosure together will form a large heat sink.

SMD Components in PCB Cavities

Although coining is an excellent use case, the typical method is to use a cavity to hold SMD components internally. This would involve defining some pads in an internal layer for an SMD component. Typically you would route into these pads in the same layer coming from outside the cavity walls, so this would be a Type 2 cavity.

A variation on this is to have an inset cavity, which is cut into one of the surface layers. This type of cavity is probably most common and is used to reduce the overall z-axis height of the board. An example image showing SMD components in a Type 2 inset cavity is shown below.

Configuring Cavities in Your PCB Layout

Unfortunately, cavities are not popular enough for CAD vendors to have created a “cavity” object in PCB layout tools. But if you want to include a cavity in your design, you can do it with an internal mechanical layer in the PCB layout.

To get started, you first need to select a routing tool radius and use this to set the corner radius of your cavity outline. Draw the outline in a new mechanical layer in your PCB Editor. Name the mechanical layer something recognizable, like “CavityLayer”.

Once the cavity outline is drawn and the appropriate radius is applied, you need to apply clearances around that outline (see below). From this outline, you could use a keepout to prevent anything from appearing in the cavity region (basic Type 1 cavity). If you are clearing copper pour from inside the cavity, you could use a polygon cutout region and size it larger than the cavity outline to account for clearance and routing tolerance.

There are four design rules to follow regarding cavities:

Clearances: Make sure to treat the outline of a cavity like a board cutout regarding clearances and tolerances.
Routing: You can route above/beneath the cavity region on other layers, but only blind/buried vias can be used in the cavity region.
Keepouts: Consider placing a keepout in the cavity region that matches the cavity boundary.
Edge plating: If you’re designing a Type 3 cavity, or Type 2 with edge plating, apply a negative clearance around the cavity edge.

Fabrication Notes for Cavities

If you followed the advice above and placed your cavity in a mechanical layer, you can also export that cavity definition into standard fabrication data (Gerbers or ODB++). When you create your outputs, make sure to include the mechanical layer for your cavity in your Gerber export.

Once the cavity is defined in your design, make sure to include a fabrication note that clearly states the fabrication needs for the cavity. When writing the fabrication note, make sure to include the following information:

The starting and ending layers for the cavity (L2 and L3 in my example)
The Gerber file containing the cavity routing path
The routing tool radius
The required tolerance on the routing path (usually +/- 10 mils)
The cavity Type as defined in the IPC-6012F standard

Because your fabricator generally won’t look at your native board files, it’s important to clearly specify this data in your fabrication documentation. If there is an option to include special notes on your quote form, make sure to copy the fabrication note there too.

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About Author

Zachariah Peterson has an extensive technical background in academia and industry. He currently provides research, design, and marketing services to companies in the electronics industry. Prior to working in the PCB industry, he taught at Portland State University and conducted research on random laser theory, materials, and stability. His background in scientific research spans topics in nanoparticle lasers, electronic and optoelectronic semiconductor devices, environmental sensors, and stochastics. His work has been published in over a dozen peer-reviewed journals and conference proceedings, and he has written 2000+ technical articles on PCB design for a number of companies. He is a member of IEEE Photonics Society, IEEE Electronics Packaging Society, American Physical Society, and the Printed Circuit Engineering Association (PCEA). He previously served as a voting member on the INCITS Quantum Computing Technical Advisory Committee working on technical standards for quantum electronics, and he currently serves on the IEEE P3186 Working Group focused on Port Interface Representing Photonic Signals Using SPICE-class Circuit Simulators.