PDN Analyzer User Guide

June 7, 2017

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How do you currently ensure that adequate copper has been provided from your voltage sources to your printed circuit loads? Is voltage drop across the PDN too large and causing loads to be starved? In a typical PCB design process, these questions often go unanswered, but engineers need to prevent excessive voltage drop across the PDN. With Altium’s PDN Analyzer, designers can spot excessive voltage drop and prevent excessive temperature rise in a printed circuit board layout.


The most powerful platform for PCB design and analysis. You can perform DC analysis of a PDN with Altium’s PDN Analyzer.

Your PDN in your circuit board is responsible for delivering the voltage from a power supply to downstream voltage regulator modules. These modules are part of power regulation and distribution to downstream components, but your PCB layout will determine how voltage and power will be lost throughout your board. A DC analysis of a PDN can help you answer these questions and many more.

There are some important questions that DC analysis of a PDN can help answer:

  • Are my vias large enough and are they located near a hot spot?
  • Will the PDN shapes cause high voltage drop and current in a specific region?
  • What part of my design is most likely to heat (burn) up?
  • Will voltage drop across the PDN reduce supply voltage?

The PDN Analyzer extension in Altium Designer gives you the analysis features you need to perform DC analysis of a PDN and identify any design changes to prevent power loss. Here’s how you can use the PDN Analyzer in Altium Designer to determine DC power drop problems in your PCB layout.

What is PDN Analysis?

Not long ago, digital design was dominated by large form factors – desktop personal computers and large servers, for instance. In those designs, entire metal layers could be dedicated to power delivery, ensuring minimal voltage drop between the source and loads. A digital designer only ensured the DC power delivery was “adequate,” with little thought about optimizing the power delivery shapes to minimize their area and layers.

Every design needs to provide enough power for all chips on a printed circuit board. The most critical step in doing this is to provide adequate copper for DC power delivery. Voltage drop (a.k.a. IR-drop) occurs in any conductor and is dissipated as heat. DC analysis of a PDN in a circuit board allows PCB designers to spot voltage drop visually in simulation results from their PCB layout.

Setting up DC Analysis of a PDN

Setting up a PDN starts with defining voltage sources and a power bus in your layout. The schematic below shows a regulator module that can be defined within a PDN.

DC analysis of a PDN with decoupling capacitors

VCCINT (1.8 V) from U4 to U1 for use in a PDN simulation.

This schematic is set up in a block diagram that shows the topology of the PDN, which includes your circuit board power source, ground, and voltage regulator modules which deliver power to various loads (memory, microcontrollers, etc.). All loads are tied to the same power and ground rails. Each portion of the PDN in your diagram, including the load regions, is generated as a network of multiple components in your PCB layout and schematics; you won’t have to manually define each load section in the PDN topology. Since we are working with a DC analysis of a PDN, decoupling capacitors are treated as open circuits and are not included in the network analysis.

DC analysis of a PDN with voltage regulator modules

A voltage regulator module as a source and 2 load networks in a PDN.

When you run first the simulation, the PDN analysis tools provides a visual map showing the voltage drop and current from the source to the loads due to the resistivity of the power net. The image below shows a layer primarily dedicated to power delivery, and we can see that this layer is broken up into many sections (nets) delivering unique voltages around the design. The decoupling capacitor C3 is included in the board and we can see where it connects to ground, as well as the voltage that developes across the capacitor. The single track from U4 to the FPGA voltage ring is the largest source of voltage drop. Only 10 mV of drop between U4 (1.7 V, was derated by 5% from the nominal 1.8 V) and U1 (1.69 V).

Voltage drop map from a power source a single load

Voltage drop map from a power source to load nets.

A DC PDN analysis tool should be capable of providing the DC voltage for a device using the ground voltage at that device as the reference voltage. The voltage relative to an arbitrary “ground” point (such as the voltage source) is often meaningless. The currents in the ground shape may induce significant voltage on the ground net, and this must be comprehended in the DC analysis of the power delivery network.

Analyzing Your DC PDN Analysis Results

When your PDN analysis is finished, you’ll be able to determine excessive temperature rise in your PDN by examining the current density. If you switch to Current Density and view the GND net, you may be able to spot peninsulas and islands in the GND shape, as indicated by their blue color (no current flow). When you spot these regions, you may be able to remove small portions of the ground plane if you do not need large interplane capacitance or internal shielding.

Identifying peninsulas and islands in the ground plane with DC analysis of a PDN

Identifying peninsulas and islands in the ground plane.

Current Density and Temperature Rise

The IPC 2152 standard provides a standard relationship between the minimum required trace or copper width for a desired temperature rise and given current density. PCB designers can compare their simulated PDN current density results to the requirements in the IPC 2152 specification to estimate the temperature rise in their conductors. PCB designers can also use the resistivity of copper (1.7・10-8 m/S for pure copper) to determine the temperature rise throughout the PDN.

Current density map of power net in Altium Designer

A current density map helps you verify that your board complies with IPC 2152 standards.

Comprehensive Tools for PCB Design and Analysis

As digital circuit board designs continuously increase in density and complexity, it’s more difficult and critical than ever to fully understand the impact of design decisions on voltage and current distribution in your PDN. The most productive workflow will include PDN analysis features alongside a schematic editor, CAD layout tools for circuit boards, and simulation features. Rather than discovering PDN failure when testing prototypes, today’s PCB designers need a way to accurately identify and resolve PDN issues at design time.

DC Analysis with the PDN Analyzer in Altium Designer

With the PDN Analyzer powered by CST® in Altium Designer®, PDN analysis is an approachable and intuitive process for every PCB designer, regardless of their experience level. This powerful extension takes data directly from your layout to run powerful simulations, and it’s accessible alongside all your other printed circuit design tools.

DC analysis of a PDN in Altium Designer

Screenshot of the PDN Analyzer in Altium Designer.

When you’re looking for the best software package for circuit design, PCB layout, and DC voltage drop analysis, Altium Designer and the PDN Analyzer extension include everything you need to visualize DC power integrity in 2D and 3D. You can identify areas in your PCB layout that need modification before you manufacture your board. Everything PCB designers need is accessible in a single application with Altium Designer.

Altium Designer on Altium 365 delivers an unprecedented amount of integration to the electronics industry until now relegated to the world of software development, allowing designers to work from home and reach unprecedented levels of efficiency.

We have only scratched the surface of what is possible to do with Altium Designer on Altium 365. You can check the product page for a more in-depth feature description or one of the On-Demand Webinars.


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